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* fix the default va_arg expansion (in the realignment case) to not implicitlyChris Lattner2010-10-101-1/+1
| | | | | | truncate the stack pointer to 32-bits on a 64-bit machine. llvm-svn: 116169
* ComputeLinearIndex doesn't need its TLI argument.Dan Gohman2010-10-061-4/+2
| | | | llvm-svn: 115792
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-19/+1
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
* Use a more efficient lowering of uint64_t --> float that can take advantage ↵Owen Anderson2010-10-051-6/+28
| | | | | | | | | of hardware signed integer conversion without having to do a double cast (uint64_t --> double --> float). This is based on the algorithm from compiler_rt's __floatundisf for X86-64. llvm-svn: 115634
* This DAG combine BRCOND transformation can look pass truncate of the operand:Evan Cheng2010-10-041-13/+18
| | | | | | | | | | | | | | | | | | | | // %a = ... // %b = and i32 %a, 2 // %c = srl i32 %b, 1 // brcond i32 %c ... // // into // // %a = ... // %b = and i32 %a, 2 // %c = setcc eq %b, 0 // brcond %c ... Make sure it restores local variable N1, which corresponds to the condition operand if it fails to match. This apparently breaks TCE but since that backend isn't in the tree I don't have a test for it. llvm-svn: 115571
* Fix code gen crash reported in PR 8235. We still lose debug info for the ↵Devang Patel2010-10-011-0/+3
| | | | | | unused argument here. This is a known limitation recorded debuginfo-tests/trunk/dbg-declare2.ll function 'f6' test case. llvm-svn: 115323
* typoGabor Greif2010-10-011-1/+1
| | | | llvm-svn: 115310
* fix typoChris Lattner2010-10-011-1/+1
| | | | llvm-svn: 115300
* fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350Chris Lattner2010-10-011-0/+9
| | | | llvm-svn: 115294
* Massive rewrite of MMX: Dale Johannesen2010-09-301-0/+60
| | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
* When isel is emitting instructions for an x86 target without CMOV, the CFG isJakob Stoklund Olesen2010-09-303-1/+24
| | | | | | | | | | | | | | | | | edited during emission. If the basic block ends in a switch that gets lowered to a jump table, any phis at the default edge were getting updated wrong. The jump table data structure keeps a pointer to the header blocks that wasn't getting updated after the MBB is split. This bug was exposed on 32-bit Linux when disabling critical edge splitting in codegen prepare. The fix is to uipdate stale MBB pointers whenever a block is split during emission. llvm-svn: 115191
* Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng2010-09-291-17/+17
| | | | | | pipeline forwarding path. llvm-svn: 115098
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
| | | | llvm-svn: 114999
* Don't try to make a vector of x86mmx; this won't work,Dale Johannesen2010-09-271-2/+4
| | | | | | and asserts. llvm-svn: 114843
* Fix for test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll crash.John Thompson2010-09-241-0/+20
| | | | llvm-svn: 114767
* Get rid of pop_macro warnings on MSVC.Michael J. Spencer2010-09-241-3/+5
| | | | llvm-svn: 114750
* Revert 114634 for now since buildbot claim it broke Clang self-hosting. I ↵Evan Cheng2010-09-231-4/+6
| | | | | | doubt it but it's possible it's exposing another bug somewhere. llvm-svn: 114681
* Fix VS 2010 build.Oscar Fuentes2010-09-231-4/+4
| | | | | | Patch by Nathan Jeffords! llvm-svn: 114661
* Follow up to r114630. Do not optimize away unconditional branch following a ↵Evan Cheng2010-09-231-6/+4
| | | | | | conditional one. llvm-svn: 114634
* SDISel should not optimize a unconditional branch following a conditional branchEvan Cheng2010-09-231-4/+5
| | | | | | | | | | | | when the unconditional branch destination is the fallthrough block. The canonicalization makes it easier to allow optimizations on DAGs to invert conditional branches. The branch folding pass (and AnalyzeBranch) will clean up the unnecessary unconditional branches later. This is one of the patches leading up to disabling codegen prepare critical edge splitting. llvm-svn: 114630
* A select between a constant and zero, when fed by a bit test, can be efficientlyOwen Anderson2010-09-221-0/+29
| | | | | | | lowered using a series of shifts. Fixes <rdar://problem/8285015>. llvm-svn: 114599
* Fixed pr20314-2.c failure, added E, F, p constraint letters.John Thompson2010-09-211-6/+17
| | | | llvm-svn: 114490
* Rework passing parent pointers into complexpatterns, I forgotChris Lattner2010-09-211-27/+35
| | | | | | | | that complex patterns are matched after the entire pattern has a structural match, therefore the NodeStack isn't in a useful state when the actual call to the matcher happens. llvm-svn: 114489
* If only user of a vreg is an copy instruction to export copy of vreg out of ↵Devang Patel2010-09-211-0/+23
| | | | | | | | | current basic block then insert DBG_VALUE so that debug value of the variable is also transfered to new vreg. Testcase is in r114476. This fixes radar 8412415. llvm-svn: 114478
* correct this logic.Chris Lattner2010-09-211-2/+2
| | | | llvm-svn: 114474
* Reimplement r114460 in target-independent DAGCombine rather than ↵Owen Anderson2010-09-211-0/+14
| | | | | | | | | target-dependent, by using the predicate to discover the number of sign bits. Enhance X86's target lowering to provide a useful response to this query. llvm-svn: 114473
* just like they can opt into getting the root of the pattern beingChris Lattner2010-09-211-1/+5
| | | | | | | matched, allow ComplexPatterns to opt into getting the parent node of the operand being matched. llvm-svn: 114472
* finish pushing MachinePointerInfo through selectiondags. At this point,Chris Lattner2010-09-212-16/+7
| | | | | | | I think I've audited all uses, so it should be dependable for address spaces, and the pointer+offset info should also be accurate when there. llvm-svn: 114464
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-215-34/+25
| | | | llvm-svn: 114461
* Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON loadBob Wilson2010-09-211-1/+2
| | | | | | and store intrinsics are represented with MemIntrinsicSDNodes. llvm-svn: 114454
* eliminate an old SelectionDAG::getTruncStore method, propagatingChris Lattner2010-09-215-83/+63
| | | | | | MachinePointerInfo around more. llvm-svn: 114452
* eliminate last SelectionDAG::getLoad old entrypoint, on to stores.Chris Lattner2010-09-213-22/+7
| | | | llvm-svn: 114450
* fix the code that infers SV info to be correct when dealingChris Lattner2010-09-211-28/+53
| | | | | | with an indexed load/store that has an offset in the index. llvm-svn: 114449
* propagate MachinePointerInfo through various uses of the oldChris Lattner2010-09-216-261/+245
| | | | | | SelectionDAG::getExtLoad overload, and eliminate it. llvm-svn: 114446
* continue MachinePointerInfo'izing, eliminating use of one of the oldChris Lattner2010-09-218-192/+192
| | | | | | getLoad overloads. llvm-svn: 114443
* convert dagcombine off the old form of getLoad. This fixes several bugs Chris Lattner2010-09-211-16/+18
| | | | | | with SVOffset computation. llvm-svn: 114442
* simplify DAGCombiner::SimplifySelectOps step #2/2.Chris Lattner2010-09-211-55/+53
| | | | llvm-svn: 114437
* substantially reduce indentation and simplify DAGCombiner::SimplifySelectOps.Chris Lattner2010-09-211-85/+76
| | | | | | no functionality change (step #1) llvm-svn: 114436
* a few more trivial updates. This fixes PerformInsertVectorEltInMemory to notChris Lattner2010-09-212-15/+13
| | | | | | | pass a completely incorrect SrcValue, which would result in a miscompile with combiner-aa. llvm-svn: 114411
* reimplement memcpy/memmove/memset lowering to use MachinePointerInfoChris Lattner2010-09-212-29/+54
| | | | | | | instead of srcvalue/offset pairs. This corrects SV info for mem operations whose size is > 32-bits. llvm-svn: 114401
* add overloads for SelectionDAG::getLoad, getStore, getTruncStore that take aChris Lattner2010-09-211-18/+47
| | | | | | | MachinePointerInfo. Among other virtues, this doesn't silently truncate the svoffset to 32-bits. llvm-svn: 114399
* simplify interface to SelectionDAG::getMemIntrinsicNode, making it take a ↵Chris Lattner2010-09-212-6/+6
| | | | | | MachinePointerInfo llvm-svn: 114397
* chagne interface to SelectionDAG::getAtomic to take a MachinePointerInfo,Chris Lattner2010-09-212-12/+4
| | | | | | eliminating some weird "infer a frame address" logic which was dead. llvm-svn: 114396
* don't implicitly drop the offset of a machinememoperand when legalizing atomics.Chris Lattner2010-09-211-2/+2
| | | | llvm-svn: 114395
* force clients of MachineFunction::getMachineMemOperand to provide aChris Lattner2010-09-211-7/+8
| | | | | | | MachinePointerInfo, propagating the type out a level of API. Remove the old MachineFunction::getMachineMemOperand impl. llvm-svn: 114393
* When TCO is turned on, it is possible to end up with aliasing FrameIndex's. ↵Owen Anderson2010-09-201-2/+13
| | | | | | | | | | | | Therefore, CombinerAA cannot assume that different FrameIndex's never alias, but can instead use MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing. This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll when CombinerAA is enabled, modulo a different register allocation sequence. llvm-svn: 114348
* Revert r114312 while I sort out some issues.Owen Anderson2010-09-191-1/+1
| | | | llvm-svn: 114313
* Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know,Owen Anderson2010-09-191-1/+1
| | | | | | | r114268 fixed the last of the blockers to enabling it. I will be monitoring for failures. llvm-svn: 114312
* Invert the logic of reachesChainWithoutSideEffects(). What we want to check ↵Owen Anderson2010-09-181-7/+7
| | | | | | | | | | is that there is NO path to the destination containing side effects, not that SOME path contains no side effects. In practice, this only manifests with CombinerAA enabled, because otherwise the chain has little to no branching, so "any" is effectively equivalent to "all". llvm-svn: 114268
* Check bb to ensure that alloca is in separate basic block.Devang Patel2010-09-151-7/+9
| | | | | | This fixes funcargs.exp regression reported by gdb testsuite. llvm-svn: 113992
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