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* [patchpoint] Add support for symbolic patchpoint targets to SelectionDAG and theLang Hames2015-04-222-19/+27
| | | | | | | | | | | | X86 backend. The code generated for symbolic targets is identical to the code generated for constant targets, except that a relocation is emitted to fix up the actual target address at link-time. This allows IR and object files containing patchpoints to be cached across JIT-invocations where the target address may change. llvm-svn: 235483
* DebugInfo: Drop rest of DIDescriptor subclassesDuncan P. N. Exon Smith2015-04-211-5/+3
| | | | | | | Delete the remaining subclasses of (the already deleted) `DIDescriptor`. Part of PR23080. llvm-svn: 235404
* DebugInfo: Assert dbg.declare/value insts are validDuncan P. N. Exon Smith2015-04-213-9/+8
| | | | | | | | | | Remove early returns for when `getVariable()` is null, and just assert that it never happens. The Verifier already confirms that there's a valid variable on these intrinsics, so we should assume the debug info isn't broken. I also updated a check for a `!dbg` attachment, which the Verifier similarly guarantees. llvm-svn: 235400
* Re-land r235154-r235156 under the existing -sehprepare flagReid Kleckner2015-04-212-8/+68
| | | | | | | | Keep the old SEH fan-in lowering on by default for now, since projects rely on it. This will make it easy to test this change with a simple flag flip. llvm-svn: 235399
* CONCAT_VECTOR of BUILD_VECTOR - minor fixSimon Pilgrim2015-04-211-0/+12
| | | | | | | | Fixed issue with the combine of CONCAT_VECTOR of 2 BUILD_VECTOR nodes - the optimisation wasn't ensuring that the scalar operands of both nodes were the same type/size for implicit truncation. Test case spotted by Patrik Hagglund llvm-svn: 235371
* Fix generic shift expansion when shift amount is 0Pawel Bylica2015-04-211-7/+9
| | | | | | | | | | | | | | | | | | | | | Summary: This fixes http://llvm.org/bugs/show_bug.cgi?id=16439. This is one possible way to approach this. The other would be to split InL>>(nbits-Amt) into (InL>>(nbits-1-Amt))>>1, which is also valid since since we only need to care about Amt up nbits-1. It's hard to tell which one is better since the shift might be expensive if this stage of expansion is not yet a legal machine integer, whereas comparisons with zero are relatively cheap at all sizes, but more expensive than a shift if the shift is on a legal machine type. Patch by Keno Fischer! Test Plan: regression test from http://reviews.llvm.org/D7752 Reviewers: chfast, resistor Reviewed By: chfast, resistor Subscribers: sanjoy, resistor, chfast, llvm-commits Differential Revision: http://reviews.llvm.org/D4978 llvm-svn: 235370
* Refactoring and enhancement to FMA combine.Olivier Sallenave2015-04-201-171/+369
| | | | llvm-svn: 235344
* DAGCombine: Remove redundant NaN checks around ISD::FSQRTTom Stellard2015-04-201-0/+35
| | | | | | | | This folds: (select (setcc x, -0.0, *lt), NaN, (fsqrt x)) -> ( fsqrt x) llvm-svn: 235333
* [InlineAsm] Remove EarlyClobber on registers that are also inputsHal Finkel2015-04-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an inline asm call has an output register marked as early-clobber, but that same register is also an input operand, what should we do? GCC accepts this, and is documented to accept this for read/write operands saying, "Furthermore, if the earlyclobber operand is also a read/write operand, then that operand is written only after it's used." For write-only operands, the situation seems less clear, but I have at least one existing codebase that assumes this will work, in part because it has syscall macros like this: ({ \ register uint64_t r0 __asm__ ("r0") = (__NR_ ## name); \ register uint64_t r3 __asm__ ("r3") = ((uint64_t) (arg0)); \ register uint64_t r4 __asm__ ("r4") = ((uint64_t) (arg1)); \ register uint64_t r5 __asm__ ("r5") = ((uint64_t) (arg2)); \ __asm__ __volatile__ \ ("sc" \ : "=&r"(r0),"=&r"(r3),"=&r"(r4),"=&r"(r5) \ : "0"(r0), "1"(r3), "2"(r4), "3"(r5) \ : "r6","r7","r8","r9","r10","r11","r12","cr0","memory"); \ r3; \ }) Furthermore, with register aliases and subregister relationships that only the backend knows about, rejecting this in the frontend seems like a difficult proposition (if we wanted to do so). However, keeping the early-clobber flag on the INLINEASM MI does not work for us, because it will cause the register's live interval to end to soon (so it will not appear defined to be used as an input). Fortunately, fixing this does not seem hard: When forming the INLINEASM MI, check to see if any of the early-clobber outputs are also inputs, and if so, remove the early-clobber flag. llvm-svn: 235283
* Fix build errors introduced by r235215Pirama Arumuga Nainar2015-04-173-2/+6
| | | | | | | | | | | | | | | Summary: - Handle TypePromoteFloat in switch statements - Move an expression into an assert to avoid unused variable in non-assert builds. Reviewers: srhines, ab Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9086 llvm-svn: 235220
* Add support to promote f16 to f32Pirama Arumuga Nainar2015-04-175-0/+514
| | | | | | | | | | | | | | Summary: This patch adds legalization support to operate on FP16 as a load/store type and do operations on it as floats. Tests for ARM are added to test/CodeGen/ARM/fp16-promote.ll Reviewers: srhines, t.p.northover Differential Revision: http://reviews.llvm.org/D8755 llvm-svn: 235215
* Fix TRUNCATE splitting helper logic.James Molloy2015-04-172-11/+15
| | | | | | | | | This is a followon to r233681 - I'd misunderstood the semantics of FTRUNC, and had confused it with (FP_ROUND ..., 0). Thanks for Ahmed Bougacha for his post-commit review! llvm-svn: 235191
* Revert r235154-r235156, they cause asserts when building win64 code ↵Nico Weber2015-04-172-78/+65
| | | | | | (http://crbug.com/477988) llvm-svn: 235170
* [SEH] Reimplement x64 SEH using WinEHPrepareReid Kleckner2015-04-172-65/+78
| | | | | | | | | | | | | | | | This now emits simple, unoptimized xdata tables for __C_specific_handler based on the handlers listed in @llvm.eh.actions calls produced by WinEHPrepare. This adds support for running __finally blocks when exceptions are thrown, and removes the old landingpad fan-in codepath. I ran some manual execution tests on small basic test cases with and without optimization, as well as on Chrome base_unittests, which uses a small amount of SEH. I'm sure there are bugs, and we may need to revert. llvm-svn: 235154
* Revert the switch lowering change (r235101, r235103, r235106)Hans Wennborg2015-04-163-897/+760
| | | | | | Looks like it broke the sanitizer-ppc64-linux1 build. Reverting for now. llvm-svn: 235108
* Switch lowering: extract jump tables and bit tests before building binary ↵Hans Wennborg2015-04-163-760/+897
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tree (PR22262) This is a major rewrite of the SelectionDAG switch lowering. The previous code would lower switches as a binary tre, discovering clusters of cases suitable for lowering by jump tables or bit tests as it went along. To increase the likelihood of finding jump tables, the binary tree pivot was selected to maximize case density on both sides of the pivot. By not selecting the pivot in the middle, the binary trees would not always be balanced, leading to performance problems in the generated code. This patch rewrites the lowering to search for clusters of cases suitable for jump tables or bit tests first, and then builds the binary tree around those clusters. This way, the binary tree will always be balanced. This has the added benefit of decoupling the different aspects of the lowering: tree building and jump table or bit tests finding are now easier to tweak separately. For example, this will enable us to balance the tree based on profile info in the future. The algorithm for finding jump tables is O(n^2), whereas the previous algorithm was O(n log n) for common cases, and quadratic only in the worst-case. This doesn't seem to be major problem in practice, e.g. compiling a file consisting of a 10k-case switch was only 30% slower, and such large switches should be rare in practice. Compiling e.g. gcc.c showed no compile-time difference. If this does turn out to be a problem, we could limit the search space of the algorithm. This commit also disables all optimizations during switch lowering in -O0. Differential Revision: http://reviews.llvm.org/D8649 llvm-svn: 235101
* TRUNCATE constant folding - minor fix for rL233224Simon Pilgrim2015-04-161-1/+4
| | | | | | Fix for test case found by James Molloy - TRUNCATE of constant build vectors can be more simply achieved by simply replacing with a new build vector node with the truncated value type - no need to touch the scalar operands at all. llvm-svn: 235079
* [CodeGen] Re-apply r234809 (concat of scalars), with an x86_mmx fix.Ahmed Bougacha2015-04-161-0/+66
| | | | | | | | | | | | | | | | | | | | | The only type that isn't an integer, isn't floating point, and isn't a vector; ladies and gentlemen, the gift that keeps on giving: x86_mmx! Fixes PR23246. Original message (reverted in r235062): [CodeGen] Combine concat_vectors of scalars into build_vector. Combine something like: (v8i8 concat_vectors (v2i8 bitcast (i16)) x4) into: (v8i8 (bitcast (v4i16 BUILD_VECTOR (i16) x4))) If any of the scalars are floating point, use that throughout. Differential Revision: http://reviews.llvm.org/D8948 llvm-svn: 235072
* DebugInfo: Gut DIScope, DIEnumerator and DISubrangeDuncan P. N. Exon Smith2015-04-161-2/+2
| | | | | | The only class the still has API left is `DIDescriptor` itself. llvm-svn: 235067
* Revert r234809 because it caused PR23246.Nick Lewycky2015-04-161-60/+0
| | | | llvm-svn: 235062
* [WinEH] Try to make the MachineFunction CFG more accurateReid Kleckner2015-04-151-42/+65
| | | | | | | | | | | | This avoids emitting code for unreachable landingpad blocks that contain calls to llvm.eh.actions and indirectbr. It's also a first step towards unifying the SEH and WinEH lowering codepaths. I'm keeping the old fan-in lowering of SEH around until the preparation version works well enough that we can switch over without breaking existing users. llvm-svn: 235037
* Add range iterators for post order and inverse post order. Use themDaniel Berlin2015-04-151-2/+1
| | | | llvm-svn: 235026
* DebugInfo: Gut DIVariable and DIGlobalVariableDuncan P. N. Exon Smith2015-04-141-1/+1
| | | | | | | | | | Gut all the non-pointer API from the variable wrappers, except an implicit conversion from `DIGlobalVariable` to `DIDescriptor`. Note that if you're updating out-of-tree code, `DIVariable` wraps `MDLocalVariable` (`MDVariable` is a common base class shared with `MDGlobalVariable`). llvm-svn: 234840
* [CodeGen] Combine concat_vectors of scalars into build_vector.Ahmed Bougacha2015-04-131-0/+60
| | | | | | | | | | | | | Combine something like: (v8i8 concat_vectors (v2i8 bitcast (i16)) x4) into: (v8i8 (bitcast (v4i16 BUILD_VECTOR (i16) x4))) If any of the scalars are floating point, use that throughout. Differential Revision: http://reviews.llvm.org/D8948 llvm-svn: 234809
* SelectionDAG: Stop using DIVariable::isInlinedFnArgument()Duncan P. N. Exon Smith2015-04-131-1/+3
| | | | | | | | | | | | | | | | | | Instead of calling the somewhat confusingly-named `DIVariable::isInlinedFnArgument()`, do the check directly here. There's possibly a small functionality change here: instead of `dyn_cast<>`'ing `DV->getScope()` to `MDSubprogram`, I'm looking up the scope chain for the actual subprogram. I suspect that this is a no-op for function arguments so in practise there isn't a real difference. I've also added a `FIXME` to check the `inlinedAt:` chain instead, since I wonder if that would be more reliable than the `MDSubprogram::describes()` function. Since this was the only user of `DIVariable::isInlinedFnArgument()`, delete it. llvm-svn: 234799
* Revert revisions r234755, r234759, r234760Jan Vesely2015-04-131-32/+0
| | | | | | | | | | | Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)" Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO" Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB" Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll on hexagon, nvptx, and r600. Revert while I investigate. llvm-svn: 234768
* Allow memory intrinsics to be tail callsKrzysztof Parzyszek2015-04-133-16/+44
| | | | llvm-svn: 234764
* DAGCombiner: Fix crash in select(select) opt.Matthias Braun2015-04-131-2/+2
| | | | | | | | | In case of different types used for the condition of the selects the select(select) -> select(and) normalisation cannot be performed. See also: http://reviews.llvm.org/D7622 llvm-svn: 234763
* Remove default in fully-covered switch (to fix Clang -Werror ↵David Blaikie2015-04-131-1/+0
| | | | | | -Wcovered-switch-default) llvm-svn: 234760
* LegalizeDAG: Try to use Overflow operations when expanding ADD/SUBJan Vesely2015-04-131-0/+33
| | | | | | | | | | v2: consider BooleanContents when processing overflow Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewers: resistor, jholewinsky (nvidia parts) Differential Revision: http://reviews.llvm.org/D6340 llvm-svn: 234755
* Remove empty non-virtual destructors or mark them =default when non-publicBenjamin Kramer2015-04-111-1/+0
| | | | | | These add no value but can make a class non-trivially copyable. NFC. llvm-svn: 234688
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-114-4/+4
| | | | | | | | | | | | | | The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' \ -j=32 -fix -format http://reviews.llvm.org/D8925 llvm-svn: 234679
* Reduce dyn_cast<> to isa<> or cast<> where possible.Benjamin Kramer2015-04-102-8/+8
| | | | | | No functional change intended. llvm-svn: 234586
* [WinEHPrepare] Don't rely on the order of IRDavid Majnemer2015-04-101-5/+9
| | | | | | | | | | The IPToState table must be emitted after we have generated labels for all functions in the table. Don't rely on the order of the list of globals. Instead, utilize WinEHFuncInfo to tell us how many catch handlers we expect to outline. Once we know we've visited all the catch handlers, emit the cppxdata. llvm-svn: 234566
* [AArch64] Promote f16 operations to f32.Ahmed Bougacha2015-04-101-3/+52
| | | | | | | | | | | | | | | | | | | | For the most common ones (such as fadd), we already did the promotion. Do the same thing for all the others. Currently, we'll just crash/assert on all these operations, as there's no hardware or libcall support whatsoever. f16 (half) is specified as an interchange - not arithmetic - format, and is expected to be promoted to single-precision for arithmetic operations. While there, teach the legalizer about promoting some of the (mostly floating-point) operations that we never needed before. Differential Revision: http://reviews.llvm.org/D8648 See related discussion on the thread for: http://reviews.llvm.org/D8755 llvm-svn: 234550
* [CodeGen] Combine concat_vector of trunc'd scalar to scalar_to_vector.Ahmed Bougacha2015-04-091-3/+13
| | | | | | | | | | | | | | We already do: concat_vectors(scalar, undef) -> scalar_to_vector(scalar) When the scalar is legal. When it's not, but is a truncated legal scalar, we can also do: concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar) Which is equivalent, since the upper lanes are undef anyway. While there, teach the combine to look at more than 2 operands. Differential Revision: http://reviews.llvm.org/D8883 llvm-svn: 234530
* Revert "Refactoring and enhancement to FMA combine."Rafael Espindola2015-04-091-361/+172
| | | | | | This reverts commit r234513. It was failing on the bots. llvm-svn: 234518
* Refactoring and enhancement to FMA combine.Olivier Sallenave2015-04-091-172/+361
| | | | llvm-svn: 234513
* [DAGCombine] Fix a bug in MergeConsecutiveStores.Akira Hatanaka2015-04-081-20/+21
| | | | | | | | | | | | | | | | | | | | | The bug manifests when there are two loads and two stores chained as follows in a DAG, (ld v3f32) -> (st f32) -> (ld v3f32) -> (st f32) and the stores' values are extracted from the preceding vector loads. MergeConsecutiveStores would replace the first store in the chain with the merged vector store, which would create a cycle between the merged store node and the last load node that appears in the chain. This commits fixes the bug by replacing the last store in the chain instead. rdar://problem/20275084 Differential Revision: http://reviews.llvm.org/D8849 llvm-svn: 234430
* CodeGen: Stop using DIDescriptor::is*() and auto-castingDuncan P. N. Exon Smith2015-04-066-17/+9
| | | | | | Same as r234255, but for lib/CodeGen and lib/Target. llvm-svn: 234258
* Use sext in fast isel.Rafael Espindola2015-04-061-1/+1
| | | | | | | | | | | | | | | | | | Fast isel used to zero extends immediates to 64 bits. This normally goes unnoticed because the value is truncated to 32 bits for output. Two cases were it is noticed: * We fail to use smaller encodings. * If the original constant was smaller than i32. In the tests using i1 constants, codegen would change to use -1, which is fine (and matches what regular isel does) since only the lowest bit is then used. Instead, this patch then changes the ir to use i8 constants, which looks more like what clang produces. llvm-svn: 234249
* [WinEH] Don't sink allocas into child handlersReid Kleckner2015-04-061-2/+4
| | | | | | | | | | The uselist isn't enough to infer anything about the lifetime of such allocas. If we want to re-add this optimization, we will need to leverage lifetime markers to do it. Fixes PR23122. llvm-svn: 234196
* [DAGCombiner] Add support for FCEIL, FFLOOR and FTRUNC vector constant foldingSimon Pilgrim2015-04-062-6/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D8715 llvm-svn: 234179
* [DAGCombiner] Merge FMUL Scalar and Vector constant canonicalization to RHS. ↵Simon Pilgrim2015-04-051-8/+2
| | | | | | NFCI. llvm-svn: 234118
* less space; NFCSanjay Patel2015-04-041-1/+0
| | | | llvm-svn: 234106
* [DAGCombiner] Canonicalize vector constants for ADD/MUL/AND/OR/XOR ↵Simon Pilgrim2015-04-041-6/+11
| | | | | | | | re-association Scalar integers are commuted to move constants to the RHS for re-association - this ensures vectors do the same. llvm-svn: 234092
* [WinEH] Fill out CatchHigh in the TryBlockMapDavid Majnemer2015-04-031-4/+2
| | | | | | Now all fields in the WinEH xdata have been filled out. llvm-svn: 234067
* [WinEH] Fill out .xdata for catch objectsDavid Majnemer2015-04-032-7/+5
| | | | | | | This add support for catching an exception such that an exception object available to the catch handler will be initialized by the runtime. llvm-svn: 234062
* [WinEH] Sink UnwindHelp completely out of IRDavid Majnemer2015-04-031-11/+0
| | | | | | | | We don't need to represent UnwindHelp in IR. Instead, we can use the knowledge that we are emitting the parent function to decide if we should create the UnwindHelp stack object. llvm-svn: 234061
* [WinEH] Handle nested landing pads in outlined catch handlersAndrew Kaylor2015-04-031-28/+0
| | | | | | Differential Revision: http://reviews.llvm.org/D8596 llvm-svn: 234041
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