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* Let printf do the formatting instead aligning strings ourselves.Benjamin Kramer2011-10-161-1/+1
| | | | | | While at it, merge some format strings. llvm-svn: 142140
* Move the legalization of vector loads and stores into LegalizeVectorOps. In someNadav Rotem2011-10-152-183/+123
| | | | | | cases we need the second type-legalization pass in order to support all cases. llvm-svn: 142060
* Clear out the landing pad to call site map for each function.Bill Wendling2011-10-151-0/+1
| | | | | | | This isn't put into the 'clear()' method because the information needs to stick around (at least for a little bit) after the selection DAG is built. llvm-svn: 142032
* Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4".Jim Grosbach2011-10-141-1/+1
| | | | | | Pointed out by George Russell. llvm-svn: 141956
* Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen2011-10-121-0/+12
| | | | | | | | | | | | | The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. llvm-svn: 141833
* Use a utility from MathExtras to clarify a check and avoid undefined ↵Eli Friedman2011-10-121-1/+1
| | | | | | behavior. Based on patch by Ahmed Charles. llvm-svn: 141829
* Fix a thinko that Nick noticed. The previous code actually worked asDan Gohman2011-10-121-1/+1
| | | | | | intended, but only by accident. llvm-svn: 141779
* Use an existing function.Jakob Stoklund Olesen2011-10-121-10/+2
| | | | llvm-svn: 141763
* Formatting.Eric Christopher2011-10-111-2/+1
| | | | llvm-svn: 141728
* Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem2011-10-111-0/+25
| | | | llvm-svn: 141667
* Add support for legalization of vector trunc-store where the saved scalar ↵Nadav Rotem2011-10-111-13/+13
| | | | | | type is illegal (for example, v2i16 on systems where the smallest store size is i32) llvm-svn: 141661
* Cleanup the trunc-store legalization code and add asserts.Nadav Rotem2011-10-111-68/+87
| | | | llvm-svn: 141659
* Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling2011-10-071-2/+8
| | | | | | do. This will be useful later on with the new SJLJ stuff. llvm-svn: 141416
* Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman2011-10-062-67/+0
| | | | | | with this patch. llvm-svn: 141333
* Modify the mapping from landing pad to call sites to accept more than one callBill Wendling2011-10-053-3/+6
| | | | | | site. llvm-svn: 141226
* Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling2011-10-051-7/+7
| | | | llvm-svn: 141221
* Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen2011-10-052-27/+52
| | | | | | | | | | | | EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. llvm-svn: 141207
* Simplify INSERT_SUBREG emission.Jakob Stoklund Olesen2011-10-051-27/+19
| | | | | | | | | | | | | | The register class created by INSERT_SUBREG and SUBREG_TO_REG must be legal and support the SubIdx sub-registers. The new getSubClassWithSubReg() hook can compute that. This may create INSERT_SUBREG instructions defining a larger register class than the sub-register being inserted. That is OK, RegisterCoalescer will constrain the register class as needed when it eliminates the INSERT_SUBREG instructions. llvm-svn: 141198
* Create a mapping between the landing pad basic block and the call site index ↵Bill Wendling2011-10-042-0/+5
| | | | | | for later use. llvm-svn: 141125
* Moved type construction out of the loop and added an assert on the legality ↵Nadav Rotem2011-10-011-10/+10
| | | | | | of the type. Formatted lines to the 80 char limit. llvm-svn: 140952
* When inferring the pointer alignment, if the global doesn't have an initializerBill Wendling2011-09-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | and the alignment is 0 (i.e., it's defined globally in one file and declared in another file) it could get an alignment which is larger than the ABI allows for that type, resulting in aligned moves being used for unaligned loads. For instance, in file A.c: struct S s; In file B.c: struct { // something long }; extern S s; void foo() { struct S p = s; // ... } this copy is a 'memcpy' which is turned into a series of 'movaps' instructions on X86. But this is wrong, because 'struct S' has alignment of 4, not 16. llvm-svn: 140902
* Promote comment to doxycomment. Adjust whitespace. No functionality change.Nick Lewycky2011-09-301-4/+3
| | | | llvm-svn: 140899
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-301-1/+2
| | | | | | It will soon need the context. llvm-svn: 140896
* Clean up uses of switch instructions so they are not dependent on the ↵Eli Friedman2011-09-291-2/+2
| | | | | | operand ordering. Patch by Stepan Dyatkovskiy. llvm-svn: 140803
* Use the local we already set up.Eric Christopher2011-09-291-1/+1
| | | | llvm-svn: 140745
* Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.Bill Wendling2011-09-281-1/+2
| | | | llvm-svn: 140678
* Create and use an llvm.eh.sjlj.functioncontext intrinsic.Bill Wendling2011-09-281-0/+8
| | | | | | | | This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. llvm-svn: 140676
* Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().Jim Grosbach2011-09-271-2/+2
| | | | | | Naming conventions consistency. No functional change. llvm-svn: 140636
* Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.Nadav Rotem2011-09-272-10/+12
| | | | | | Add a new method: getAnyExtOrTrunc and use it to replace the manual check. llvm-svn: 140603
* Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,Nadav Rotem2011-09-271-10/+1
| | | | | | while the decision is to bit-pack small values. llvm-svn: 140601
* [vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENTNadav Rotem2011-09-251-2/+7
| | | | | | | | | SDNodes may return values which are wider than the incoming element types. In this patch we fix the integer promotion of these nodes. Fixes spill-q.ll when running -promote-elements. llvm-svn: 140471
* Implement Duncan's suggestion to use the result of getSetCCResultType if it ↵Nadav Rotem2011-09-241-4/+9
| | | | | | | | | | is legal (this is always the case for scalars), otherwise use the promoted result type. Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled. llvm-svn: 140464
* [Vector-Select] Address one of the problems in 10902.Nadav Rotem2011-09-241-1/+10
| | | | | | | | | | When generating the trunc-store of i1's, we need to use the vector type and not the scalar type. This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when running with -promote-elements. llvm-svn: 140463
* Tweak the handling of MERGE_VALUES nodes: remove the need forDuncan Sands2011-09-236-51/+43
| | | | | | | | | DecomposeMERGE_VALUES to "know" that results are legalized in a particular order, by passing it the number of the result being legalized (the type legalization core provides this, it just needs to be passed on). llvm-svn: 140373
* Vector-Select: Address one of the problems in pr10902. Add handling for theNadav Rotem2011-09-232-0/+43
| | | | | | | | | | integer-promotion of CONCAT_VECTORS. Test: test/CodeGen/X86/widen_shuffle-1.ll This patch fixes the above tests (when running in with -promote-elements). llvm-svn: 140372
* Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman2011-09-221-0/+3
| | | | | | worklist, as it may be possible to perform further optimization on them. llvm-svn: 140349
* Constrain register classes instead of emitting copies.Jakob Stoklund Olesen2011-09-221-3/+5
| | | | | | | | | | | Sometimes register class constraints are trivial, like GR32->GR32_NOSP, or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual register instead of emitting a copy in these cases. Normally, these copies are handled by the coalescer. This saves some coalescer work. llvm-svn: 140340
* [VECTOR-SELECT] Address one of the bugs in pr10902.Nadav Rotem2011-09-211-0/+2
| | | | | | | Vector SetCC result types need to be type-legalized. This code worked before because scalar result types are known to be legal. llvm-svn: 140249
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-212-6/+5
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* Add a DAGCombine for subvector extracts to remove useless chains ofBruno Cardoso Lopes2011-09-201-0/+32
| | | | | | | subvector inserts and extracts. Initial patch by Rackover, Zvi with some tweak done by me. llvm-svn: 140204
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-202-2/+8
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-202-8/+2
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* whitespaceAndrew Trick2011-09-202-30/+30
| | | | llvm-svn: 140133
* white space cleanupsNadav Rotem2011-09-181-5/+4
| | | | llvm-svn: 139994
* Some legalization fixes for atomic load and store.Eli Friedman2011-09-153-1/+29
| | | | llvm-svn: 139851
* Add integer promotion support for vselectNadav Rotem2011-09-142-0/+10
| | | | llvm-svn: 139692
* Fix check for unaligned load/store so it doesn't catch over-aligned load/store.Eli Friedman2011-09-131-2/+2
| | | | llvm-svn: 139649
* Error out on CodeGen of unaligned load/store. Fix test so it isn't ↵Eli Friedman2011-09-131-2/+9
| | | | | | accidentally testing that case. llvm-svn: 139641
* Fix the assertion which checks the size of the input operand.Nadav Rotem2011-09-131-1/+1
| | | | llvm-svn: 139633
* Add vselect target support for targets that do not support blend but do supportNadav Rotem2011-09-132-2/+45
| | | | | | xor/and/or (For example SSE2). llvm-svn: 139623
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