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* Assign ordering to nodes created in ExpandNode. Only roughly 1/2 of the functionBill Wendling2009-12-221-84/+237
| | | | | | is finished. llvm-svn: 91942
* Assign ordering to SDNodes in PromoteNode. Also fixing a subtle bug where BSWAPBill Wendling2009-12-222-15/+83
| | | | | | was using "Tmp1" in the first getNode call instead of Node->getOperand(0). llvm-svn: 91936
* Allow 0 as an order number. Don't assign an order to formal arguments.Bill Wendling2009-12-222-21/+11
| | | | llvm-svn: 91920
* Report an error for bad inline assembly, where the value passed for anBob Wilson2009-12-221-2/+6
| | | | | | "indirect" operand is not a pointer. llvm-svn: 91913
* Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling2009-12-225-49/+147
| | | | | | | | return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. llvm-svn: 91880
* Add SDNode ordering to inlined asm and VA functions.Bill Wendling2009-12-221-28/+78
| | | | llvm-svn: 91876
* Adding more assignment of ordering to SDNodes. This time in the "call" andBill Wendling2009-12-221-32/+66
| | | | | | generic copy functions. llvm-svn: 91872
* Add ordering of SDNodes to LowerCallTo.Bill Wendling2009-12-221-19/+44
| | | | llvm-svn: 91866
* Now add ordering to SDNodes created by the massive intrinsic lowering function.Bill Wendling2009-12-221-100/+183
| | | | llvm-svn: 91863
* To make things interesting, I added MORE code to set the ordering ofBill Wendling2009-12-221-32/+387
| | | | | | SDNodes. This time in the load/store and limited-precision code. llvm-svn: 91860
* Add more plumbing to assign ordering to SDNodes. Have the "getValue" methodBill Wendling2009-12-211-59/+133
| | | | | | | assign the ordering when called. Combine some of the ordering assignments to keep things simple. llvm-svn: 91857
* More ordering plumbing. This time for GEP. I need to remember to assignBill Wendling2009-12-211-4/+32
| | | | | | orderings to values returned by getValue(). llvm-svn: 91850
* Another incremental check-in for assigning ordering to SDNodes. This time forBill Wendling2009-12-211-25/+75
| | | | | | shuffle and insert vector. llvm-svn: 91847
* Assign ordering to more instructions. Incremental check-in.Bill Wendling2009-12-211-57/+156
| | | | llvm-svn: 91846
* - Add a bit more plumbing assigning an order to SDNodes.Bill Wendling2009-12-212-9/+32
| | | | | | - Modify the "dump" method to emit the order of an SDNode. llvm-svn: 91845
* First wave of plumbing for assigning an ordering to SDNodes. This takes care ofBill Wendling2009-12-211-28/+43
| | | | | | a lot of the branching instructions. llvm-svn: 91838
* Place SDNodeOrdering.h in the directory it's used.Bill Wendling2009-12-212-1/+59
| | | | llvm-svn: 91834
* Use 4-arg getVTList) variant instead of generic one, when possibleAnton Korobeynikov2009-12-191-0/+1
| | | | llvm-svn: 91744
* Changes from review:Bill Wendling2009-12-184-143/+67
| | | | | | | | | | | - Move DisableScheduling flag into TargetOption.h - Move SDNodeOrdering into its own header file. Give it a minimal interface that doesn't conflate construction with storage. - Move assigning the ordering into the SelectionDAGBuilder. This isn't used yet, so there should be no functional changes. llvm-svn: 91727
* Increase opportunities to optimize (brcond (srl (and c1), c2)).Evan Cheng2009-12-181-1/+28
| | | | llvm-svn: 91717
* Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson2009-12-181-1/+1
| | | | | | | | The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. llvm-svn: 91649
* Introduce EVT::getHalfSizedIntegerVT() for use in ExpandUnalignedStore() inKen Dyck2009-12-171-6/+3
| | | | | | | | | | | | | | LegalizeDAG.cpp. Unlike the code it replaces, which simply decrements the simple type by one, getHalfSizedIntegerVT() searches for the smallest simple integer type that is at least half the size of the type it is called on. This approach has the advantage that it will continue working if a new value type (such as i24) is added to MVT. Also, in preparation for new value types, remove the assertions that non-power-of-2 8-bit-mutiple types are Extended when legalizing extload and truncstore operations. llvm-svn: 91614
* Fix a comment grammaro.Bob Wilson2009-12-171-2/+2
| | | | llvm-svn: 91584
* Revert this dag combine change:Evan Cheng2009-12-171-13/+0
| | | | | | | | Fold (zext (and x, cst)) -> (and (zext x), cst) DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping. llvm-svn: 91574
* Reapply r91392, it was only unmasking the bug, and since TOT is still broken ↵Daniel Dunbar2009-12-163-29/+155
| | | | | | having it reverted does no good. llvm-svn: 91560
* Revert "Initial work on disabling the scheduler. This is a work in progress, andDaniel Dunbar2009-12-163-155/+29
| | | | | | | this", this broke llvm-gcc bootstrap for release builds on x86_64-apple-darwin10. llvm-svn: 91533
* Make 91378 more conservative.Evan Cheng2009-12-151-1/+11
| | | | | | | 1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest. 2. If the shift is a left shift, make sure the original shift cannot shift out bits. llvm-svn: 91399
* Initial work on disabling the scheduler. This is a work in progress, and thisBill Wendling2009-12-153-29/+155
| | | | | | | | | | | | | | | stuff isn't used just yet. We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2' flags. The hypothesis is that the people who use these flags know what they are doing, and have hand-optimized the C code to reduce latencies and other conflicts. The idea behind our scheme to turn off scheduling is to create a map "on the side" during DAG generation. It will order the nodes by how they appeared in the code. This map is then used during scheduling to get the ordering. llvm-svn: 91392
* Fold (zext (and x, cst)) -> (and (zext x), cst).Evan Cheng2009-12-151-0/+13
| | | | llvm-svn: 91380
* Propagate zest through logical shift.Evan Cheng2009-12-151-0/+10
| | | | llvm-svn: 91378
* Fix integer cast code to handle vector types.Dan Gohman2009-12-142-20/+45
| | | | llvm-svn: 91362
* Fix this to properly clear the FastISel debug location. Thanks toDan Gohman2009-12-141-1/+1
| | | | | | Bill for spotting this! llvm-svn: 91355
* Fix weird typo which leads to unallocated memory access for nodes with 4 ↵Anton Korobeynikov2009-12-131-1/+1
| | | | | | results. llvm-svn: 91233
* Delete an unnecessary line. The VTSDNode on a SIGN_EXTEND_REG is neverDan Gohman2009-12-111-1/+0
| | | | | | a vector type. llvm-svn: 91181
* Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman2009-12-117-32/+84
| | | | llvm-svn: 91158
* Fix the result type of SELECT nodes lowered from Select instructions withDan Gohman2009-12-111-1/+1
| | | | | | aggregate return values. This fixes PR5754. llvm-svn: 91145
* Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng2009-12-091-0/+6
| | | | | | isl lowering code. llvm-svn: 90925
* Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's ↵Evan Cheng2009-12-093-44/+44
| | | | | | primary used by selectdag passes. llvm-svn: 90922
* Infer alignment for non-fixed stack object.Evan Cheng2009-12-091-3/+4
| | | | llvm-svn: 90919
* Add const qualifier.Evan Cheng2009-12-091-1/+1
| | | | llvm-svn: 90918
* Refactor InferAlignment out of DAGCombine.Evan Cheng2009-12-092-45/+46
| | | | llvm-svn: 90917
* Truncate the arguments of llvm.frameaddress / llvm.returnaddress intrinsics ↵Anton Korobeynikov2009-12-072-1/+13
| | | | | | from i32 to platform's largest native type llvm-svn: 90741
* Remove old DBG_LABEL code.Dan Gohman2009-12-051-8/+0
| | | | llvm-svn: 90669
* Remove the unused DisableLegalizeTypes option and related code.Dan Gohman2009-12-052-52/+47
| | | | llvm-svn: 90668
* Don't blindly set the debug location for PHI node copies.Dan Gohman2009-12-051-3/+3
| | | | llvm-svn: 90637
* Make TargetSelectInstruction protected and called from FastISel.cppDan Gohman2009-12-052-7/+9
| | | | | | instead of SelectionDAGISel.cpp. llvm-svn: 90636
* The debug information for an LLVM Instruction applies to that InstructionDan Gohman2009-12-051-33/+57
| | | | | | | and that Instruction only. Implement this by setting the "current debug position" back to Unknown after processing each instruction. llvm-svn: 90632
* Add note about a subtle bug in this code. Does not effect the mainDuncan Sands2009-12-041-0/+6
| | | | | | architectures that LLVM targets, because they don't use this code. llvm-svn: 90564
* Fix ExpandShiftWithUnknownAmountBit, which was completely bogus.Duncan Sands2009-12-031-37/+38
| | | | | | | | | | | | Pointed out by Javier Martinez (who also provided a patch). Since this logic is not used on (for example) x86, I guess nobody noticed. Tested by generating SHL, SRL, SRA on various choices of i64 for all possible shift amounts, and comparing with gcc. Since I did this on x86-32, I had to force the use of ExpandShiftWithUnknownAmountBit. What I'm saying here is that I don't have a testcase I can add to the repository. llvm-svn: 90482
* Don't pull vector sext through both hands of a logical operation, since ↵Nate Begeman2009-12-031-2/+8
| | | | | | | | | doing so prevents the fusion of vector sext and setcc into vsetcc. Add a testcase for the above transformation. Fix a bogus use of APInt noticed while tracking this down. llvm-svn: 90423
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