| Commit message (Collapse) | Author | Age | Files | Lines |
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multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
llvm-svn: 27334
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CodeGen/Generic/vector-identity-shuffle.ll
llvm-svn: 27317
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UnitTests/Vector/sumarray-dbl on PPC.
Now all UnitTests/Vector/* tests pass on PPC.
llvm-svn: 27299
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This fixes UnitTests/Vector/simple.c with altivec.
llvm-svn: 27298
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to:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 12, r32
;;
ldfs f8 = [r8]
mov ar.pfs = r3
br.ret.sptk.many rp
instead of:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 28, r32
adds r9 = 24, r32
adds r10 = 20, r32
adds r11 = 16, r32
;;
ldfs f6 = [r8]
;;
ldfs f6 = [r9]
adds r8 = 12, r32
adds r9 = 8, r32
adds r14 = 4, r32
;;
ldfs f6 = [r10]
;;
ldfs f6 = [r11]
ldfs f8 = [r8]
;;
ldfs f6 = [r9]
;;
ldfs f6 = [r14]
;;
ldfs f6 = [r32]
mov ar.pfs = r3
br.ret.sptk.many rp
llvm-svn: 27297
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vector.ll:test_extract_elt2 into:
_test_extract_elt2:
lfd f1, 32(r3)
blr
instead of:
_test_extract_elt2:
lfd f0, 56(r3)
lfd f0, 48(r3)
lfd f0, 40(r3)
lfd f1, 32(r3)
lfd f0, 24(r3)
lfd f0, 16(r3)
lfd f0, 8(r3)
lfd f0, 0(r3)
blr
llvm-svn: 27296
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Generic/vector.ll:test_extract_elt on non-sse X86 systems.
llvm-svn: 27294
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needs to be promoted or expanded. Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.
llvm-svn: 27293
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decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
llvm-svn: 27280
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handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.
llvm-svn: 27278
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llvm-svn: 27274
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Handle constantpacked vectors with constantexpr elements.
This fixes CodeGen/Generic/vector-constantexpr.ll
llvm-svn: 27241
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sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).
The later is not canonical form, and prevents the PPC splat pattern from
matching. For a particular splat, we go from generating this:
li r10, lo16(LCPI1_0)
lis r11, ha16(LCPI1_0)
lvx v3, r11, r10
vperm v3, v2, v2, v3
to generating:
vspltw v3, v2, 3
llvm-svn: 27236
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llvm-svn: 27235
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vector_shuffle node. For this:
void test(__m128 *res, __m128 *A, __m128 *B) {
*res = _mm_unpacklo_ps(*A, *B);
}
we now produce this code:
_test:
movl 8(%esp), %eax
movaps (%eax), %xmm0
movl 12(%esp), %eax
unpcklps (%eax), %xmm0
movl 4(%esp), %eax
movaps %xmm0, (%eax)
ret
instead of this:
_test:
subl $76, %esp
movl 88(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, (%esp)
movaps %xmm0, 32(%esp)
movss 4(%esp), %xmm0
movss 32(%esp), %xmm1
unpcklps %xmm0, %xmm1
movl 84(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, 16(%esp)
movaps %xmm0, 48(%esp)
movss 20(%esp), %xmm0
movss 48(%esp), %xmm2
unpcklps %xmm0, %xmm2
unpcklps %xmm1, %xmm2
movl 80(%esp), %eax
movaps %xmm2, (%eax)
addl $76, %esp
ret
GCC produces this (with -fomit-frame-pointer):
_test:
subl $12, %esp
movl 20(%esp), %eax
movaps (%eax), %xmm0
movl 24(%esp), %eax
unpcklps (%eax), %xmm0
movl 16(%esp), %eax
movaps %xmm0, (%eax)
addl $12, %esp
ret
llvm-svn: 27233
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llvm-svn: 27232
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llvm-svn: 27231
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llvm-svn: 27229
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llvm-svn: 27228
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llvm-svn: 27224
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value. Split them into separate enums.
llvm-svn: 27201
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llvm-svn: 27192
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llvm-svn: 27182
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llvm-svn: 27181
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llvm-svn: 27173
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llvm-svn: 27171
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llvm-svn: 27169
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floating point cases.
llvm-svn: 27165
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llvm-svn: 27164
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manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
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llvm-svn: 27155
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llvm-svn: 27147
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llvm-svn: 27146
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false
llvm-svn: 27131
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llvm-svn: 27130
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llvm-svn: 27128
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llvm-svn: 27089
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llvm-svn: 27071
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llvm-svn: 27063
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using a splat for {1.0,1.0,1.0,1.0}
llvm-svn: 27055
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llvm-svn: 27053
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Legalize intrinsic nodes.
llvm-svn: 27036
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llvm-svn: 27035
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llvm-svn: 27032
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the target can handle it). Issue two SCALAR_TO_VECTOR ops followed by a
VECTOR_SHUFFLE to select from the two vectors.
llvm-svn: 27023
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llvm-svn: 27020
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CodeGen/Generic/vector.ll:test_cast_2.
llvm-svn: 26999
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llvm-svn: 26988
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llvm-svn: 26972
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llvm-svn: 26965
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