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* Add a hackaround for PR7993 which is causing failures on x86 builders that ↵Chris Lattner2010-08-261-0/+2
| | | | | | lack sse2. llvm-svn: 112175
* implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.Chris Lattner2010-08-262-66/+93
| | | | llvm-svn: 112171
* zap dead code.Chris Lattner2010-08-262-37/+0
| | | | llvm-svn: 112155
* remove some llvmcontext arguments that are now dead post-refactoring.Chris Lattner2010-08-253-6/+4
| | | | llvm-svn: 112104
* Change handling of illegal vector types to widen when possible instead of Chris Lattner2010-08-252-46/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
* Fix comment.Devang Patel2010-08-251-4/+3
| | | | llvm-svn: 112086
* Remove dead argument.Devang Patel2010-08-252-6/+4
| | | | llvm-svn: 112085
* split the vector case of getCopyFromParts out to its own function,Chris Lattner2010-08-241-81/+102
| | | | | | no functionality change. llvm-svn: 111994
* split the vector case out of getCopyToParts into its own function. NoChris Lattner2010-08-241-117/+126
| | | | | | functionality change. llvm-svn: 111990
* tidy up, reduce indentationChris Lattner2010-08-242-127/+123
| | | | llvm-svn: 111982
* Fix some GCC warnings by providing a virtual destructor in the base of a classChandler Carruth2010-08-231-1/+1
| | | | | | | hierarchy with virtual methods and using llvm_unreachable to properly indicate unreachable states which would otherwise leave variables uninitialized. llvm-svn: 111803
* If the target says that an extending load is not legal, regardless of whetherBob Wilson2010-08-191-7/+12
| | | | | | | | | | | it involves specific floating-point types, legalize should expand an extending load to a non-extending load followed by a separate extend operation. For example, we currently expand SEXTLOAD to EXTLOAD+SIGN_EXTEND_INREG (and assert that EXTLOAD should always be supported). Now we can expand that to LOAD+SIGN_EXTEND. This is needed to allow vector SIGN_EXTEND and ZERO_EXTEND to be used for NEON. llvm-svn: 111586
* Make fast scheduler handle asm clobbers correctly.Dale Johannesen2010-08-171-21/+53
| | | | | | PR 7882. Follows suggestion by Amaury Pouly, thanks. llvm-svn: 111306
* Fix typo.Eric Christopher2010-08-171-1/+1
| | | | llvm-svn: 111223
* Add missing null check reported by Amaury Pouly.Evan Cheng2010-08-101-2/+3
| | | | llvm-svn: 110649
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Eliminate unnecessary empty string literals.Dan Gohman2010-08-041-1/+1
| | | | llvm-svn: 110183
* Prefix `next' iterator operation with `llvm::'.Oscar Fuentes2010-08-021-1/+1
| | | | | | | | Fixes potential ambiguity problems on VS 2010. Patch by nobled! llvm-svn: 110029
* PR7586: Make sure we don't claim that unknown bits are actually known in theEli Friedman2010-08-021-3/+2
| | | | | | ISD::AND case of TargetLowering::SimplifyDemandedBits. llvm-svn: 110019
* Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctlyEli Friedman2010-07-301-6/+3
| | | | | | | check the range of the constant when optimizing a comparison between a constant and a sign_extend_inreg node. llvm-svn: 109854
* Fix a crash in the dag combiner caused by ↵Nate Begeman2010-07-271-2/+10
| | | | | | | | ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR. llvm-svn: 109519
* It's better to have the arrays, which would trigger the creation of stackBill Wendling2010-07-271-1/+9
| | | | | | | | | protectors, to be near the stack protectors on the stack. Accomplish this by tagging the stack object with a predicate that indicates that it would trigger this. In the prolog-epilog inserter, assign these objects to the stack after the stack protector but before the other objects. llvm-svn: 109481
* The "excess register pressure" returned by HighRegPressure() is not accurate ↵Evan Cheng2010-07-261-41/+20
| | | | | | enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling. llvm-svn: 109449
* Handle Values with no value in getCopyFromRegs.Dan Gohman2010-07-261-0/+4
| | | | llvm-svn: 109415
* Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess ↵Duncan Sands2010-07-261-1/+2
| | | | | | | | parameter) may be used uninitialized in the callers of HighRegPressure. llvm-svn: 109393
* Add comments.Evan Cheng2010-07-251-4/+16
| | | | llvm-svn: 109383
* Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts onBob Wilson2010-07-251-2/+2
| | | | | | those. Radar 8231572. llvm-svn: 109367
* Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng2010-07-242-12/+76
| | | | | | | | | | | | appropriate for targets without detailed instruction iterineries. The scheduler schedules for increased instruction level parallelism in low register pressure situation; it schedules to reduce register pressure when the register pressure becomes high. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%. llvm-svn: 109300
* - Allow target to specify when is register pressure "too high". In most cases,Evan Cheng2010-07-231-56/+124
| | | | | | | | | | | | | it's too late to start backing off aggressive latency scheduling when most of the registers are in use so the threshold should be a bit tighter. - Correctly handle live out's and extract_subreg etc. - Enable register pressure aware scheduling by default for hybrid scheduler. For ARM, this is almost always a win on # of instructions. It's runtime neutral for most of the tests. But for some kernels with high register pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by 54 and sped up by 20%. llvm-svn: 109279
* Use the proper type for shift counts. This fixes a bootstrap error.Dan Gohman2010-07-231-1/+4
| | | | llvm-svn: 109265
* DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bitsDan Gohman2010-07-231-1/+21
| | | | | | are not demanded. This often allows the anyext to be folded away. llvm-svn: 109242
* Make SDNode::dump() print a newline at the end.Dan Gohman2010-07-231-0/+1
| | | | llvm-svn: 109234
* 80-col.Eric Christopher2010-07-231-8/+12
| | | | llvm-svn: 109205
* keep in 80 colsGabor Greif2010-07-221-2/+4
| | | | llvm-svn: 109122
* mass elimination of reliance on automatic iterator dereferencingGabor Greif2010-07-222-2/+2
| | | | llvm-svn: 109103
* Re-apply r109079 with fix.Evan Cheng2010-07-221-28/+26
| | | | llvm-svn: 109083
* Revert r109079, which broke a lot of CodeGen tests.Owen Anderson2010-07-221-25/+27
| | | | llvm-svn: 109082
* Initialize RegLimit only when register pressure is being tracked.Evan Cheng2010-07-221-27/+25
| | | | llvm-svn: 109079
* More register pressure aware scheduling work.Evan Cheng2010-07-211-81/+84
| | | | llvm-svn: 109064
* Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng2010-07-212-22/+242
| | | | llvm-svn: 108991
* After a custom inserter, in a block which has constant instructions,Dan Gohman2010-07-191-0/+1
| | | | | | | update the current basic block in addition to the current insert position, so that they remain consistent. This fixes rdar://8204072. llvm-svn: 108765
* ARM has to provide its own TargetLowering::findRepresentativeClass because ↵Evan Cheng2010-07-191-6/+7
| | | | | | its scalar floating point registers alias its vector registers. llvm-svn: 108761
* Teach computeRegisterProperties() to compute "representative" register class ↵Evan Cheng2010-07-191-0/+52
| | | | | | | | for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. llvm-svn: 108735
* Remove r108639 now that it is handled by InstCombine instead.Owen Anderson2010-07-191-13/+0
| | | | llvm-svn: 108688
* Add a DAGCombine xform to fold away redundant float->double->float ↵Owen Anderson2010-07-181-0/+13
| | | | | | | | | | conversions around sqrt instructions. I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed <rdar://problem/8197504>. llvm-svn: 108639
* Propagate alloca alignment information via variable size object frameEric Christopher2010-07-171-1/+1
| | | | | | | | information. No functional change yet. llvm-svn: 108583
* Revert r108369, sorting llvm.dbg.declare information by source position,Dan Gohman2010-07-163-26/+34
| | | | | | | | | | | | | since it doesn't work for front-ends which don't emit column information (which includes llvm-gcc in its present configuration), and doesn't work for clang for K&R style variables where the variables are declared in a different order from the parameter list. Instead, make a separate pass through the instructions to collect the llvm.dbg.declare instructions in order. This ensures that the debug information for variables is emitted in this order. llvm-svn: 108538
* Use the source-order scheduler instead of the "fast" scheduler at -O0,Dan Gohman2010-07-161-1/+1
| | | | | | | because it's more likely to keep debug line information in its original order. llvm-svn: 108496
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