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* Cosmetic changes.Evan Cheng2008-03-291-24/+3
| | | | llvm-svn: 48947
* ifdef out a dead function. Should this be removed?Chris Lattner2008-03-281-0/+2
| | | | llvm-svn: 48916
* Rename getAnyLoad to getLoad is suggested by Evan.Duncan Sands2008-03-282-17/+17
| | | | llvm-svn: 48914
* Implement LegalizeTypes support for softfloat LOAD.Duncan Sands2008-03-273-78/+64
| | | | | | | | In order to handle indexed nodes I had to introduce a new constructor, and since I was there I factorized the code in the various load constructors. llvm-svn: 48894
* Avoid creating chain dependencies from CopyToReg nodes to load and storeDan Gohman2008-03-271-54/+72
| | | | | | | | | | | | | | | | | | nodes. This doesn't currently have much impact the generated code, but it does produce simpler-looking SelectionDAGs, and consequently simpler-looking ScheduleDAGs, because there are fewer spurious dependencies. In particular, CopyValueToVirtualRegister now uses the entry node as the input chain dependency for new CopyToReg nodes instead of calling getRoot and depending on the most recent memory reference. Also, rename UnorderedChains to PendingExports and pull it up from being a local variable in SelectionDAGISel::BuildSelectionDAG to being a member variable of SelectionDAGISel, so that it doesn't have to be passed around to all the places that need it. llvm-svn: 48893
* Fix spelling. Thanks, Duncan! :-)Roman Levenstein2008-03-271-1/+1
| | | | llvm-svn: 48873
* Speed-up the SumOfUnscheduledPredsOfSuccs by introducing a new functionRoman Levenstein2008-03-271-2/+25
| | | | | | | | | | called LimitedSumOfUnscheduledPredsOfSuccs. It terminates the computation after a given treshold is reached. This new function is always faster, but brings real wins only on bigger test-cases. The old function SumOfUnscheduledPredsOfSuccs is left in-place for now and therefore a warning about an unused static function is produced. llvm-svn: 48872
* Use a linked data structure for the uses lists of an SDNode, just like Roman Levenstein2008-03-266-108/+137
| | | | | | | | | | | | | LLVM Value/Use does and MachineRegisterInfo/MachineOperand does. This allows constant time for all uses list maintenance operations. The idea was suggested by Chris. Reviewed by Evan and Dan. Patch is tested and approved by Dan. On normal use-cases compilation speed is not affected. On very big basic blocks there are compilation speedups in the range of 15-20% or even better. llvm-svn: 48822
* Fixed some spelling errors. Thanks, Duncan!Roman Levenstein2008-03-261-52/+54
| | | | llvm-svn: 48819
* Some improvements related to the computation of isReachable.Roman Levenstein2008-03-261-54/+315
| | | | | | | | | | | | | | | | | | | | | | | | | This fixes Bugzilla #1835 (http://llvm.org/bugs/show_bug.cgi?id=1835). This patched is reviewed by Tanya and Dan. Dan tested and approved it. The reason for the bad performance of the old algorithm is that it is very naive and scans every time all nodes of the DAG in the worst case. This patch introduces a new algorithm based on the paper "Online algorithms for maintaining the topological order of a directed acyclic graph" by David J.Pearce and Paul H.J.Kelly. This is the MNR algorithm. It has a linear time worst-case and performs much better in most situations. The paper can be found here: http://fano.ics.uci.edu/cites/Document/Online-algorithms-for-maintaining-the-topological-order-of-a-directed-acyclic-graph.html The main idea of the new algorithm is to compute the topological ordering of the SNodes in the DAG and to maintain it even after DAG modifications. The topological ordering allows for very fast node reachability checks. Tests on very big input files with tens of thousands of instructions in a BB indicate huge speed-ups (up to 10x compilation time improvement) compared to the old version. llvm-svn: 48817
* A quick nm audit turned up several fixed tables and objects that wereDan Gohman2008-03-251-4/+4
| | | | | | | marked read-write. Use const so that they can be allocated in a read-only segment. llvm-svn: 48800
* Handle a special case xor undef, undef -> 0. Technically this should be ↵Evan Cheng2008-03-252-1/+9
| | | | | | transformed to undef. But this is such a common idiom (misuse) we are going to handle it. llvm-svn: 48792
* Fix typos.Dan Gohman2008-03-251-3/+3
| | | | llvm-svn: 48779
* Remove an unneeded test.Evan Cheng2008-03-241-1/+1
| | | | llvm-svn: 48755
* APIntify SelectionDAG's EXTRACT_ELEMENT code.Dan Gohman2008-03-241-2/+4
| | | | llvm-svn: 48726
* Another comments fixingAnton Korobeynikov2008-03-221-1/+1
| | | | llvm-svn: 48683
* Teach DAG combiner to commute commutable binary nodes in order to achieve ↵Evan Cheng2008-03-222-0/+31
| | | | | | sdisel CSE. llvm-svn: 48673
* Fix -view-sunit-dags to support cross-rc-copy nodes.Dan Gohman2008-03-211-1/+4
| | | | llvm-svn: 48664
* Introduce a new node for holding call argumentDuncan Sands2008-03-215-56/+90
| | | | | | | | | | | | | | | | | flags. This is needed by the new legalize types infrastructure which wants to expand the 64 bit constants previously used to hold the flags on 32 bit machines. There are two functional changes: (1) in LowerArguments, if a parameter has the zext attribute set then that is marked in the flags; before it was being ignored; (2) PPC had some bogus code for handling two word arguments when using the ELF 32 ABI, which was hard to convert because of the bogusness. As suggested by the original author (Nicolas Geoffray), I've disabled it for the moment. Tested with "make check" and the Ada ACATS testsuite. llvm-svn: 48640
* Check even more carefully before applying this DAGCombine transform.Christopher Lamb2008-03-201-13/+19
| | | | llvm-svn: 48580
* Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, ↵Evan Cheng2008-03-201-1/+3
| | | | | | result_size - n - m))) llvm-svn: 48578
* detabify llvm, patch by Mike Stump!Chris Lattner2008-03-202-3/+3
| | | | llvm-svn: 48577
* Fix X86's isTruncateFree to not claim that truncate to i1 is free. This ↵Christopher Lamb2008-03-191-0/+25
| | | | | | fixes Bill's testcase that failed for r48491. llvm-svn: 48542
* Temporarily revert r48491. It's breaking test/CodeGen/X86/xorl.ll.Bill Wendling2008-03-181-26/+0
| | | | llvm-svn: 48510
* Make conversions of i8/i16 to ppcf128 work.Dale Johannesen2008-03-181-10/+13
| | | | llvm-svn: 48493
* Target independent DAG transform to use truncate for field extraction + sign ↵Christopher Lamb2008-03-181-0/+26
| | | | | | extend on targets where this is profitable. Passes nightly on x86-64. llvm-svn: 48491
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-47/+28
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-3/+8
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Do not generate special entries in the dwarf ehDuncan Sands2008-03-141-6/+2
| | | | | | table for nounwind calls. llvm-svn: 48373
* Simplify using getIntPtrConstant.Duncan Sands2008-03-141-5/+3
| | | | llvm-svn: 48355
* Tabs -> spacesNate Begeman2008-03-141-14/+23
| | | | | | | Use getIntPtrConstant in a couple places to shorten stuff up Handle splitting vector shuffles with undefs in the mask llvm-svn: 48351
* Livein copy scheduling fixes: do not coalesce physical register copies, ↵Evan Cheng2008-03-141-112/+42
| | | | | | correctly determine the safe location to insert the copies. llvm-svn: 48348
* More APInt-ification.Dan Gohman2008-03-135-67/+77
| | | | llvm-svn: 48344
* Experimental scheduler change to schedule / coalesce the copies added for ↵Evan Cheng2008-03-121-23/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1028<def> = MOV32rr %EAX %reg1029<def> = MOV32rr %EDX %reg1030<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0] %reg1025<def> = MOV32rr %reg1029 %reg1026<def> = MOV32rr %reg1030 %reg1024<def> = MOV32rr %reg1028 The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled. With -schedule-livein-copies: entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1024<def> = MOV32rr %EAX %reg1025<def> = MOV32rr %EDX %reg1026<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0] Much better! llvm-svn: 48307
* Initial soft-float support for LegalizeTypes. I rewroteDuncan Sands2008-03-126-34/+248
| | | | | | | | | | | | | | | | | | | | | the fcopysign expansion from LegalizeDAG to get rid of what seems to be a bug: the use of sign extension means that when copying the sign bit from an f32 to an f64, the upper 32 bits of the f64 (now an i64) are set, not just the top bit... I also generalized it to work for any sized floating point types, and removed the bogosity: SDOperand Mask1 = (SrcVT == MVT::f64) ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); (here SrcNVT is an integer with the same size as SrcVT). As far as I can see this takes a 1 << 63, converts to a double, converts that to a floating point constant then converts that to an integer constant, ending up with... 1 << 63 as an integer constant! So I just generate this integer constant directly. llvm-svn: 48305
* Fix typo.Duncan Sands2008-03-121-1/+1
| | | | llvm-svn: 48295
* Don't try to extract an i32 from an f64. ThisDuncan Sands2008-03-122-12/+22
| | | | | | | | | | | | getCopyToParts problem was noticed by the new LegalizeTypes infrastructure. In order to avoid this kind of thing in the future I've added a check that EXTRACT_ELEMENT is only used with integers. Once LegalizeTypes is up and running most likely BUILD_PAIR and EXTRACT_ELEMENT can be removed, in favour of using apints instead. llvm-svn: 48294
* Clean up my own mess.Evan Cheng2008-03-121-7/+1
| | | | | | X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases. llvm-svn: 48279
* Total brain cramp.Evan Cheng2008-03-121-1/+1
| | | | llvm-svn: 48274
* Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137Anton Korobeynikov2008-03-111-1/+10
| | | | llvm-svn: 48257
* Use the correct value for InSignBit.Dan Gohman2008-03-111-1/+1
| | | | llvm-svn: 48245
* Initial codegen support for functions and calls with multiple return values.Dan Gohman2008-03-111-18/+51
| | | | llvm-svn: 48244
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-111-16/+14
| | | | | | failures. llvm-svn: 48223
* When the register allocator runs out of registers, spill a physical register ↵Evan Cheng2008-03-112-7/+6
| | | | | | around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. llvm-svn: 48218
* Some LegalizeTypes code factorization and minorDuncan Sands2008-03-115-56/+113
| | | | | | enhancements. llvm-svn: 48215
* compile: double test() {}Chris Lattner2008-03-111-1/+3
| | | | | | | | | | | | | | | | | | | | into: _test: fldz ret instead of: _test: subl $12, %esp #IMPLICIT_DEF %xmm0 movsd %xmm0, (%esp) fldl (%esp) addl $12, %esp ret llvm-svn: 48213
* variadic instructions don't have operand info for variadic arguments.Chris Lattner2008-03-111-1/+2
| | | | llvm-svn: 48208
* Generalize ExpandIntToFP to handle the case where the operand is legalDan Gohman2008-03-111-11/+22
| | | | | | | | and it's the result that requires expansion. This code is a little confusing because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type (the integer type) rather than the result type. llvm-svn: 48206
* If a register operand comes from the variadic part of a node, don'tChris Lattner2008-03-111-4/+6
| | | | | | verify the register constraint matches what the instruction expects. llvm-svn: 48205
* More APInt-ification.Dan Gohman2008-03-111-7/+7
| | | | llvm-svn: 48201
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