summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG
Commit message (Collapse)AuthorAgeFilesLines
* Use the correct shift amount type.Owen Anderson2011-02-281-1/+1
| | | | llvm-svn: 126684
* Clean whitespace.Owen Anderson2011-02-281-3/+3
| | | | llvm-svn: 126683
* Legalize support for fpextend of vector. PR9309.Duncan Sands2011-02-271-0/+2
| | | | llvm-svn: 126574
* Fix typos in the comments.Nadav Rotem2011-02-271-4/+7
| | | | llvm-svn: 126565
* Pass the graph to the DOTGraphTraits.getEdgeAttributes().Tobias Grosser2011-02-271-1/+2
| | | | | | This follows the interface of getNodeAttributes. llvm-svn: 126562
* Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize ↵Benjamin Kramer2011-02-261-0/+38
| | | | | | | | | | | legalized code for large integer arithmetic. 1. Inform users of ADDEs with two 0 operands that it never sets carry 2. Fold other ADDs or ADDCs into the ADDE if possible It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code. llvm-svn: 126557
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-256-96/+117
| | | | | | the type of the LHS. llvm-svn: 126518
* Fix formatting of debug helper string.Jim Grosbach2011-02-251-1/+1
| | | | llvm-svn: 126471
* Set NumSignBits to 1 if KnownZero/KnownOne are being zero extended. In theory itCameron Zwarich2011-02-251-0/+1
| | | | | | | | is possible to do better if the high bit is set in either KnownZero/KnownOne, but in practice NumSignBits is always 1 when we are zero extending because nothing is known about that register. llvm-svn: 126465
* We only want to zero extend the existing information if the bit width isCameron Zwarich2011-02-251-1/+1
| | | | | | actually larger. llvm-svn: 126464
* Enable support for vector sext and trunc:Nadav Rotem2011-02-241-10/+17
| | | | | | | | | | Limit the folding of any_ext and sext into the load operation to scalars. Limit the active-bits trunc optimization to scalars. Document vector trunc and vector sext in LangRef. Similar to commit 126080 (for enabling zext). llvm-svn: 126424
* Merge information about the number of zero, one, and sign bits of live-outCameron Zwarich2011-02-242-1/+122
| | | | | | | registers at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine phase. This fixes <rdar://problem/8760114>. llvm-svn: 126380
* Add a getNumSignBits() method to APInt.Cameron Zwarich2011-02-241-6/+1
| | | | llvm-svn: 126379
* Add a mechanism for invalidating the LiveOutInfo of a PHI, and use it wheneverCameron Zwarich2011-02-241-1/+18
| | | | | | a block is visited before all of its predecessors. llvm-svn: 126378
* Track blocks visited in reverse postorder.Cameron Zwarich2011-02-242-0/+5
| | | | llvm-svn: 126377
* Refactor the LiveOutInfo interface into a few methods on FunctionLoweringInfoCameron Zwarich2011-02-242-17/+9
| | | | | | and make the actual map private. llvm-svn: 126376
* Have isel visit blocks in reverse postorder rather than an undefined order. ThisCameron Zwarich2011-02-241-2/+5
| | | | | | allows for the information propagated across basic blocks to be merged at phis. llvm-svn: 126375
* Roll out r126169 and r126170 in an attempt to fix the selfhost bot.Cameron Zwarich2011-02-223-59/+9
| | | | llvm-svn: 126185
* Merge information about the number of zero, one, and sign bits of live-out ↵Cameron Zwarich2011-02-223-7/+54
| | | | | | | | | registers at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine phase. This fixes <rdar://problem/8760114>. llvm-svn: 126170
* Have isel visit blocks in reverse postorder rather than an undefined order. ThisCameron Zwarich2011-02-221-2/+5
| | | | | | allows for the information propagated across basic blocks to be merged at phis. llvm-svn: 126169
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-212-11/+2
| | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) llvm-svn: 126155
* Fix 9267; Add vector zext support.Nadav Rotem2011-02-201-1/+3
| | | | | | | | The DAGCombiner folds the zext into complex load instructions. This patch prevents this optimization on vectors since none of the supported targets knows how to perform load+vector_zext in one instruction. llvm-svn: 126080
* Do not lose debug info of an inlined function argument even if the argument ↵Devang Patel2011-02-184-14/+15
| | | | | | | | is only used through GEPs. This time with a fix that avoids using invalidated DenseMap iterator. llvm-svn: 125984
* Roll out r125794 to help diagnose the llvm-gcc-i386-linux-selfhost failure.Cameron Zwarich2011-02-184-10/+13
| | | | llvm-svn: 125830
* Do not lose debug info of an inlined function argument even if the argument ↵Devang Patel2011-02-174-13/+10
| | | | | | is only used through GEPs. llvm-svn: 125794
* Fix wrong logic in promotion of signed mul-with-overflow (I pointed this out atDuncan Sands2011-02-171-18/+12
| | | | | | | | | the time but presumably my email got lost). Examples where the previous logic got it wrong: (1) a signed i8 multiply of 64 by 2 overflows, but the high part is zero; (2) a signed i8 multiple of -128 by 2 overflows, but the high part is all ones. llvm-svn: 125748
* Swap VT and DebugLoc operands of getExtLoad() for consistency withStuart Hastings2011-02-166-53/+52
| | | | | | other getNode() methods. Radar 9002173. llvm-svn: 125665
* Refactor zero folding slightly. Clean up todo.Eric Christopher2011-02-161-22/+20
| | | | llvm-svn: 125651
* The change for PR9190 wasn't quite right. We need to avoid making theEric Christopher2011-02-161-2/+12
| | | | | | | | | transformation if we can't legally create a build vector of the correct type. Check that we can make the transformation first, and add a TODO to refactor this code with similar cases. Fixes: PR9223 and rdar://9000350 llvm-svn: 125631
* convert ConstantVector::get to use ArrayRef.Chris Lattner2011-02-151-22/+6
| | | | llvm-svn: 125537
* revert my ConstantVector patch, it seems to have made the llvm-gccChris Lattner2011-02-141-6/+22
| | | | | | builders unhappy. llvm-svn: 125504
* Switch ConstantVector::get to use ArrayRef instead of a pointer+sizeChris Lattner2011-02-141-22/+6
| | | | | | idiom. Change various clients to simplify their code. llvm-svn: 125487
* fix PR9210 by implementing some type legalization logic for Chris Lattner2011-02-142-14/+47
| | | | | | vector fp conversions. llvm-svn: 125482
* fix two comment thinkosChris Lattner2011-02-141-1/+1
| | | | llvm-svn: 125481
* Enhance ComputeMaskedBits to know that aligned frameindexesChris Lattner2011-02-132-9/+37
| | | | | | | | | | | | | | | | | have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. llvm-svn: 125470
* Revisit my fix for PR9028: the issue is that DAGCombine was Chris Lattner2011-02-134-40/+46
| | | | | | | | | generating i8 shift amounts for things like i1024 types. Add an assert in getNode to prevent this from occuring in the future, fix the buggy transformation, revert my previous patch, and document this gotcha in ISDOpcodes.h llvm-svn: 125465
* when legalizing extremely wide shifts, make sure that Chris Lattner2011-02-132-3/+9
| | | | | | | | | the shift amounts are in a suitably wide type so that we don't generate out of range constant shift amounts. This fixes PR9028. llvm-svn: 125458
* fix visitShift to properly zero extend the shift amount if the provided operandChris Lattner2011-02-131-20/+19
| | | | | | | is narrower than the shift register. Doing an anyext provides undefined bits in the top part of the register. llvm-svn: 125457
* A fix for 9165.Nadav Rotem2011-02-121-4/+9
| | | | | | | | The DAGCombiner created illegal BUILD_VECTOR operations. The patch added a check that either illegal operations are allowed or that the created operation is legal. llvm-svn: 125435
* SimplifySelectOps can only handle selects with a scalar condition. Add a checkNadav Rotem2011-02-111-0/+3
| | | | | | that the condition is not a vector. llvm-svn: 125398
* Fix #9190Nadav Rotem2011-02-111-1/+1
| | | | | | | | | | | The bug happens when the DAGCombiner attempts to optimize one of the patterns of the SUB opcode. It tries to create a zero of type v2i64. This type is legal on 32bit machines, but the initializer of this vector (i64) is target dependent. Currently, the initializer attempts to create an i64 zero constant, which fails. Added a flag to tell the DAGCombiner to create a legal zero, if we require that the pass would generate legal types. llvm-svn: 125391
* Remove comment about an argument that was removed couple of years ago.Devang Patel2011-02-071-1/+0
| | | | llvm-svn: 125054
* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-043-114/+165
| | | | | | | | | | | | | | | precisely track pressure on a selection DAG, but we can at least keep it balanced. This design accounts for various interesting aspects of selection DAGS: register and subregister copies, glued nodes, dead nodes, unused registers, etc. Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter. Note: I disabled PrescheduleNodesWithMultipleUses when register pressure is enabled, based on no evidence other than I don't think it makes sense to have both enabled. llvm-svn: 124853
* whitespaceAndrew Trick2011-02-031-18/+18
| | | | llvm-svn: 124827
* Given a pair of floating point load and store, if there are no other uses ofEvan Cheng2011-02-021-0/+65
| | | | | | | | | | | | | | | | | | | the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 llvm-svn: 124708
* Take Bill Wendling's suggestion for structuring a couple of asserts.Matt Beaumont-Gay2011-02-011-6/+6
| | | | llvm-svn: 124688
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-312-2/+11
| | | | llvm-svn: 124611
* Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.Richard Osborne2011-01-311-2/+2
| | | | llvm-svn: 124587
* Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer2011-01-301-0/+23
| | | | | | | | | | | | | | | | | | c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
* Add the missing sub identity "A-(A-B) -> B" to DAGCombine.Benjamin Kramer2011-01-291-0/+3
| | | | | | | | This happens e.g. for code like "X - X%10" where we lower the modulo operation to a series of multiplies and shifts that are then subtracted from X, leading to this missed optimization. llvm-svn: 124532
OpenPOWER on IntegriCloud