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* f16 FREM can now be legalized by promoting to f32Pete Cooper2012-04-041-0/+1
| | | | llvm-svn: 154039
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-045-142/+85
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* Remove default case from switch that was already covering all cases.Craig Topper2012-04-041-1/+0
| | | | llvm-svn: 153996
* Removed useless switch for default case when switch was covering all the ↵Pete Cooper2012-04-041-1/+0
| | | | | | enum values llvm-svn: 153984
* Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it ↵Pete Cooper2012-04-032-0/+34
| | | | | | would crash if it encountered a 1 element VSELECT. Solution is slightly more complicated than just creating a SELET as we have to mask or sign extend the vector condition if it had different boolean contents from the scalar condition. Fixes <rdar://problem/11178095> llvm-svn: 153976
* Fix an issue in SimplifySetCC() specific to vector comparisons.Chad Rosier2012-04-031-2/+10
| | | | | | | | | | | When folding X == X we need to check getBooleanContents() to determine if the result is a vector of ones or a vector of negative ones. I tried creating a test case, but the problem seems to only be exposed on a much older version of clang (around r144500). rdar://10923049 llvm-svn: 153966
* Add predicates for checking whether targets have free FNEG and FABS ↵Owen Anderson2012-04-021-3/+5
| | | | | | operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. llvm-svn: 153901
* Optimizing swizzles of complex shuffles may generate additional complex ↵Nadav Rotem2012-04-021-1/+9
| | | | | | | | | shuffles. Do not try to optimize swizzles of shuffles if the source shuffle has more than a single user, except when the source shuffle is also a swizzle. llvm-svn: 153864
* This commit contains a few changes that had to go in together.Nadav Rotem2012-04-011-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) (and also scalar_to_vector). 2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src). Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B)) 3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y). 4. Fix an X86ISelLowering optimization which was very bitcast-sensitive. Code which was previously compiled to this: movd (%rsi), %xmm0 movdqa .LCPI0_0(%rip), %xmm2 pshufb %xmm2, %xmm0 movd (%rdi), %xmm1 pshufb %xmm2, %xmm1 pxor %xmm0, %xmm1 pshufb .LCPI0_1(%rip), %xmm1 movd %xmm1, (%rdi) ret Now compiles to this: movl (%rsi), %eax xorl %eax, (%rdi) ret llvm-svn: 153848
* Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola2012-03-312-7/+13
| | | | | | | | This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. llvm-svn: 153817
* If we have a VLA that has a "use" in a metadata node that's then usedBill Wendling2012-03-301-1/+12
| | | | | | | | | | | | | | | | here but it has no other uses, then we have a problem. E.g., int foo (const int *x) { char a[*x]; return 0; } If we assign 'a' a vreg and fast isel later on has to use the selection DAG isel, it will want to copy the value to the vreg. However, there are no uses, which goes counter to what selection DAG isel expects. <rdar://problem/11134152> llvm-svn: 153705
* More debug output.Eric Christopher2012-03-281-1/+2
| | | | llvm-svn: 153571
* fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)Chris Lattner2012-03-271-2/+2
| | | | llvm-svn: 153513
* Add a debug statement.Eric Christopher2012-03-261-1/+3
| | | | llvm-svn: 153428
* Add the ability to promote legal integer VAARGs. This is required for the ↵Hal Finkel2012-03-241-1/+33
| | | | | | PPC64 SVR4 ABI. llvm-svn: 153372
* Source order scheduler should not preschedule nodes with multiple uses. ↵Evan Cheng2012-03-221-7/+11
| | | | | | rdar://11096639 llvm-svn: 153270
* Assign node orders to target intrinsics which do not produce results. ↵Evan Cheng2012-03-221-0/+6
| | | | | | rdar://11096639 llvm-svn: 153269
* [fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%Chad Rosier2012-03-221-0/+7
| | | | | | | | | execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester. This may also improve compile-time on architectures that would otherwise generate a libcall for urem (e.g., ARM) or fall back to the DAG selector. rdar://10810716 llvm-svn: 153230
* Checking a build_vector for an all-ones value.Jim Grosbach2012-03-211-5/+14
| | | | | | | | Type legalization can zero-extend the elements of the build_vector node, so, for example, we may have an <8 x i8> with i32 elements of value 255. That should return 'true' for the vector being all ones. llvm-svn: 153203
* When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper2012-03-201-0/+1
| | | | | | users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. llvm-svn: 153078
* Do everything up to generating code to try to get a register forEric Christopher2012-03-201-1/+6
| | | | | | | | | | a variable. The previous code would break the debug info changing code invariant. This will regress debug info for arguments where we elide the alloca created. Fixes rdar://11066468 llvm-svn: 153074
* Untabify.Eric Christopher2012-03-201-2/+2
| | | | llvm-svn: 153073
* Add another debugging statement here.Eric Christopher2012-03-201-0/+4
| | | | llvm-svn: 153072
* Use lookUpRegForValue here instead of duplicating the code.Eric Christopher2012-03-201-9/+2
| | | | llvm-svn: 153071
* f16 FDIV can now be legalized by promoting to f32Pete Cooper2012-03-191-1/+2
| | | | llvm-svn: 153064
* Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands2012-03-191-0/+6
| | | | llvm-svn: 153035
* Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." ↵NAKAMURA Takumi2012-03-161-1/+1
| | | | | | | | | for workaround of g++-4.4's miscompilation. It caused MSP430DAGToDAGISel::SelectIndexedBinOp() to be miscompiled. When two ReplaceUses()'s are expanded as inline, vtable in base class is stored to latter (ISelUpdater)ISU. llvm-svn: 152877
* We actually handle AllocaInst via getRegForValue below just fine.Eric Christopher2012-03-151-1/+1
| | | | | | Part of rdar://8905263 llvm-svn: 152845
* Add some debugging output into fast isel as well.Eric Christopher2012-03-151-2/+6
| | | | llvm-svn: 152844
* Add another debug statement.Eric Christopher2012-03-151-1/+3
| | | | llvm-svn: 152843
* When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, ↵Nadav Rotem2012-03-151-0/+4
| | | | | | add the new node into the work list because there is a potential for further optimizations. llvm-svn: 152784
* Add a xform to the DAG combiner.Bill Wendling2012-03-151-0/+17
| | | | | | | | | | | | Transform: (fsub x, (fadd x, y)) -> (fneg y) and (fsub x, (fadd y, x)) -> (fneg y) if 'unsafe math' is specified. <rdar://problem/7540295> llvm-svn: 152777
* Insert the debugging instructions in one fell-swoop so that it doesn't call theBill Wendling2012-03-141-7/+8
| | | | | | | expensive "getFirstTerminator" call. This reduces the time of compilation in PR12258 from >10 minutes to < 10 seconds. llvm-svn: 152704
* Fortify r152675 a bit. Although I'm not able to come up with a test case ↵Evan Cheng2012-03-131-3/+11
| | | | | | that would trigger the truncation case. llvm-svn: 152678
* DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) toEvan Cheng2012-03-131-4/+19
| | | | | | | | | (i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)). rdar://11035895 llvm-svn: 152675
* Add a return type.Bill Wendling2012-03-131-1/+1
| | | | llvm-svn: 152614
* Inline the d'tor and add an anchor instead.Bill Wendling2012-03-131-1/+1
| | | | llvm-svn: 152613
* Refactor the SelectionDAG's 'dump' methods into their own .cpp file.Bill Wendling2012-03-133-633/+632
| | | | | | No functionality change. llvm-svn: 152611
* llvm::SwitchInstStepan Dyatkovskiy2012-03-111-1/+1
| | | | | | | Renamed methods caseBegin, caseEnd and caseDefault with case_begin, case_end, and case_default. Added some notes relative to case iterators. llvm-svn: 152532
* Give dagcombiner's worklist some inline capacity.Benjamin Kramer2012-03-101-3/+2
| | | | llvm-svn: 152454
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-082-8/+8
| | | | llvm-svn: 152301
* Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy2012-03-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*". ConstCaseIt is just a read-only iterator. CaseIt is read-write iterator; it allows to change case successor and case value. Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters. Main way of iterator usage looks like this: SwitchInst *SI = ... // intialize it somehow for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) { BasicBlock *BB = i.getCaseSuccessor(); ConstantInt *V = i.getCaseValue(); // Do something. } If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method. If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method. There are also related changes in llvm-clients: klee and clang. llvm-svn: 152297
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-076-37/+37
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-073-14/+22
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* misched preparation: modularize schedule emission.Andrew Trick2012-03-072-3/+51
| | | | | | ScheduleDAG has nothing to do with how the instructions are scheduled. llvm-svn: 152206
* misched preparation: modularize schedule printing.Andrew Trick2012-03-073-0/+17
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
* misched preparation: modularize schedule verification.Andrew Trick2012-03-075-3/+22
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
* whitespaceAndrew Trick2012-03-071-5/+5
| | | | llvm-svn: 152203
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-072-0/+7
| | | | | | Soon, ScheduleDAG will not refer to the BB. llvm-svn: 152177
* whitespaceAndrew Trick2012-03-071-3/+3
| | | | llvm-svn: 152175
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