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* Allow inlining of functions with returns_twice calls, if they have theJoerg Sonnenberger2011-12-181-1/+1
| | | | | | attribute themselve. llvm-svn: 146851
* Update DebugLoc while merging nodes at -O0.Devang Patel2011-12-152-6/+21
| | | | | | Patch by Kyriakos Georgiou! llvm-svn: 146670
* Don't try to form FGETSIGN after legalization; it is possible in some cases, ↵Eli Friedman2011-12-151-1/+2
| | | | | | but the existing code can't do it correctly. PR11570. llvm-svn: 146630
* Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. ↵Owen Anderson2011-12-151-0/+22
| | | | | | These are already marked as illegal by default. llvm-svn: 146623
* Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.Eli Friedman2011-12-141-0/+5
| | | | llvm-svn: 146548
* [fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle Chad Rosier2011-12-131-103/+0
| | | | | | instructions that define aggregate types. llvm-svn: 146492
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-137-23/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* [fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2.Chad Rosier2011-12-131-1/+6
| | | | llvm-svn: 146453
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-121-1/+0
| | | | llvm-svn: 146409
* [fast-isel] SelectInsertValue seems to be causing miscompiles for ARM. ↵Chad Rosier2011-12-101-0/+1
| | | | | | Disable while I investigate. llvm-svn: 146331
* Typo.Chad Rosier2011-12-101-1/+1
| | | | llvm-svn: 146327
* [fast-isel] Add support for selecting insertvalue.Chad Rosier2011-12-091-0/+102
| | | | | | rdar://10530851 llvm-svn: 146276
* Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.Eli Friedman2011-12-091-4/+3
| | | | llvm-svn: 146219
* Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson2011-12-083-15/+43
| | | | | | can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. llvm-svn: 146193
* Add rather verbose stats for fast-isel failures.Chad Rosier2011-12-081-0/+153
| | | | llvm-svn: 146186
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-082-10/+67
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* Fix a bug in the integer-promotion of bitcast operations on vector types.Nadav Rotem2011-12-081-1/+1
| | | | | | | We must not issue a bitcast operation for integer-promotion of vector types, because the location of the values in the vector may be different. llvm-svn: 146150
* Make sure we correctly set LiveRegGens when a call is unscheduled. ↵Eli Friedman2011-12-071-1/+8
| | | | | | <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling. llvm-svn: 146087
* Fix an assertion in the scheduler. PR11386. No testcase included because ↵Eli Friedman2011-12-071-3/+2
| | | | | | it's rather delicate. llvm-svn: 146083
* These global variables aren't thread-safe, STATISTIC is. Andy Trick tells meNick Lewycky2011-12-071-66/+12
| | | | | | that he isn't using these any more, so just delete them. llvm-svn: 146076
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-072-2/+2
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this ↵Eli Friedman2011-12-071-1/+1
| | | | | | doesn't affect any in-tree target. llvm-svn: 146015
* Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves ↵Eli Friedman2011-12-071-13/+17
| | | | | | correctly. PR11494. llvm-svn: 145996
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+2
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Add support for vectors of pointers.Nadav Rotem2011-12-051-1/+1
| | | | llvm-svn: 145801
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-024-45/+68
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* If fast-isel fails, remove dead instructions generated during the failed Chad Rosier2011-11-291-0/+27
| | | | | | attempt. llvm-svn: 145425
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-291-10/+0
| | | | llvm-svn: 145420
* Make SelectionDAG::InferPtrAlignment use llvm::ComputeMaskedBits instead of ↵Eli Friedman2011-11-281-18/+9
| | | | | | duplicating the logic for globals. Make llvm::ComputeMaskedBits handle GlobalVariables slightly more aggressively, to match what InferPtrAlignment knew how to do. llvm-svn: 145304
* Revert r145273 and fix in SelectionDAG::InferPtrAlignment() instead.Evan Cheng2011-11-282-27/+17
| | | | | | | | | | | Conservatively returns zero when the GV does not specify an alignment nor is it initialized. Previously it returns ABI alignment for type of the GV. However, if the type is a "packed" type, then the under-specified alignments is attached to the load / store instructions. In that case, the alignment of the type cannot be trusted. rdar://10464621 llvm-svn: 145300
* DAG combine should not increase alignment of loads / stores with alignment lessEvan Cheng2011-11-281-12/+26
| | | | | | | | | than ABI alignment. These are loads / stores from / to "packed" data structures. Their alignments are intentionally under-specified. rdar://10301431 llvm-svn: 145273
* 80-column.Chad Rosier2011-11-281-2/+4
| | | | llvm-svn: 145267
* Remove dead llvm.eh.sjlj.dispatchsetup intrinsic.Bill Wendling2011-11-283-8/+0
| | | | llvm-svn: 145263
* Fix an obvious omission in the SelectionDAGBuilder where we wereChandler Carruth2011-11-221-2/+2
| | | | | | | | | | | | | dropping weights on the floor for invokes. This was impeding my writing further test cases for invoke when interacting with probabilities and block placement. No test case as there doesn't appear to be a way to test this stuff. =/ Suggestions for a test case of course welcome. I hope to be able to add test cases that indirectly cover this eventually by adding probabilities to the exceptional edge and reordering blocks as a result. llvm-svn: 145060
* When fast iseling a GEP, accumulate the offset rather than emitting a series ofChad Rosier2011-11-171-11/+35
| | | | | | | | | | | | | ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs being: (1) If we can't materialize the large constant then we'll cause fast-isel to bail. (2) Too large of an offset can't be directly encoded in the ADD resulting in a MOV+ADD. Generally not a bad thing because otherwise we would have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix for that. (3) Conversely, too low of a threshold we'll miss opportunities to coalesce ADDs. rdar://10412592 llvm-svn: 144886
* Make sure to replace the chain properly when DAGCombining a ↵Eli Friedman2011-11-161-4/+17
| | | | | | LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393. llvm-svn: 144863
* Add fast-isel stats to determine who's doing all the work, the Chad Rosier2011-11-161-0/+7
| | | | | | target-independent selector or the target-specific selector. llvm-svn: 144833
* Fix the stats collection for fast-isel. The failed count was only accountingChad Rosier2011-11-161-5/+18
| | | | | | | | | for a single miss and not all predecessor instructions that get selected by the selection DAG instruction selector. This is still not exact (e.g., over states misses when folded/dead instructions are present), but it is a step in the right direction. llvm-svn: 144832
* CONCAT_VECTORS can have more than two operands. PR11389.Eli Friedman2011-11-161-22/+12
| | | | llvm-svn: 144768
* Add a couple asserts so it will be easier to debug if we accidentally pass ↵Eli Friedman2011-11-161-0/+4
| | | | | | indexed loads/stores to the legalizer. llvm-svn: 144767
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-2/+2
| | | | llvm-svn: 144747
* GEPs with all zero indices are trivially coalesced by fast-isel. For example,Chad Rosier2011-11-151-0/+5
| | | | | | | | | | | | | %arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0 %arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134 Prior to this commit, the GEP instruction that defines %arrayidx136 thought that %arrayidx135 was a trivial kill. The GEP that defines %arrayidx135 doesn't generate any code and thus %M0 gets folded into the second GEP. Thus, we need to look through GEPs with all zero indices. rdar://10443319 llvm-svn: 144730
* Added custom lowering for load->dec->store sequence in x86 when the EFLAGS ↵Pete Cooper2011-11-151-0/+5
| | | | | | | | | | | | registers is used by later instructions. Only done for DEC64m right now. Fixes <rdar://problem/6172640> llvm-svn: 144705
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-151-2/+2
| | | | llvm-svn: 144648
* Twinify GraphWriter a little bit.Benjamin Kramer2011-11-151-1/+1
| | | | llvm-svn: 144647
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-157-7/+0
| | | | llvm-svn: 144634
* Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman2011-11-122-11/+11
| | | | | | runs. Fixes PR11029. llvm-svn: 144438
* Some cleanup and bulletproofing for node replacement in LegalizeDAG. To ↵Eli Friedman2011-11-111-57/+59
| | | | | | | | maintain LegalizeDAG invariants, whenever we a node is replaced, we must attempt to delete it, and if it still has uses after it is replaced (which can happen in rare cases due to CSE), we must revisit it. llvm-svn: 144432
* Use a bigger hammer to fix PR11314 by disabling the "forcing two-addressEvan Cheng2011-11-101-1/+5
| | | | | | | | | | | | | | | | instruction lower optimization" in the pre-RA scheduler. The optimization, rather the hack, was done before MI use-list was available. Now we should be able to implement it in a better way, perhaps in the two-address pass until a MI scheduler is available. Now that the scheduler has to backtrack to handle call sequences. Adding artificial scheduling constraints is just not safe. Furthermore, the hack is not taking all the other scheduling decisions into consideration so it's just as likely to pessimize code. So I view disabling this optimization goodness regardless of PR11314. llvm-svn: 144267
* Add check so we don't try to perform an impossible transformation. Fixes ↵Eli Friedman2011-11-091-1/+2
| | | | | | issue from PR11319. llvm-svn: 144216
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