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* Fix spelling mistakes in SelectionDAG comments. NFC.Simon Pilgrim2016-11-204-5/+5
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287487
* [SelectionDAG] Add knowbits support for CONCAT_VECTOR opcodeSimon Pilgrim2016-11-181-0/+18
| | | | llvm-svn: 287387
* Timer: Track name and description.Matthias Braun2016-11-181-19/+26
| | | | | | | | | | | | | The previously used "names" are rather descriptions (they use multiple words and contain spaces), use short programming language identifier like strings for the "names" which should be used when exporting to machine parseable formats. Also removed a unused TimerGroup from Hexxagon. Differential Revision: https://reviews.llvm.org/D25583 llvm-svn: 287369
* Fix spelling in comment. NFC.Simon Pilgrim2016-11-171-1/+1
| | | | llvm-svn: 287222
* [CMake] NFC. Updating CMake dependency specificationsChris Bieneman2016-11-171-2/+3
| | | | | | This patch updates a bunch of places where add_dependencies was being explicitly called to add dependencies on intrinsics_gen to instead use the DEPENDS named parameter. This cleanup is needed for a patch I'm working on to add a dependency debugging mode to the build system. llvm-svn: 287206
* [CodeGen] Pass references, not pointers, to MMI helpers. NFC.Ahmed Bougacha2016-11-162-3/+3
| | | | | | While there, rename them to follow the coding style. llvm-svn: 287169
* [CodeGen] Pull MMI helpers from FunctionLoweringInfo to MMI. NFC.Ahmed Bougacha2016-11-161-56/+0
| | | | | | | | | | | They're not SelectionDAG- or FunctionLoweringInfo-specific. They are, however, specific to building MMI from IR. We could make them members, but it's nice having MMI be a "simple" data structure and this logic kept separate. This also lets us reuse them from GlobalISel. llvm-svn: 287167
* Integer legalization: fix MUL expansionPawel Bylica2016-11-151-4/+4
| | | | | | | | | | | | | | | Summary: This fixes the runtime results produces by the fallback multiplication expansion introduced in r270720. For tests I created a fuzz tester that compares the results with Boost.Multiprecision. Reviewers: hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26628 llvm-svn: 286998
* Introduce TLI predicative for base-relative Jump Tables.Joerg Sonnenberger2016-11-151-1/+1
| | | | | | | | | | | For 64bit ABIs it is common practice to use relative Jump Tables with potentially different relocation bases. As the logic for the jump table itself doesn't depend on the relocation base, make it easier for targets to use the generic logic. Start by dropping the now redundant MIPS logic. Differential Revision: https://reviews.llvm.org/D26578 llvm-svn: 286951
* DAGCombiner: fix combine of trunc and selectAsaf Badouh2016-11-151-1/+1
| | | | | | | | | | | | | bugzilla: https://llvm.org/bugs/show_bug.cgi?id=29002 pr29002 Differential Revision: https://reviews.llvm.org/D26449 llvm-svn: 286938
* [SelectionDAG] Add support for vector demandedelts in BSWAP opcodesSimon Pilgrim2016-11-111-1/+2
| | | | llvm-svn: 286582
* [SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodesSimon Pilgrim2016-11-111-6/+10
| | | | llvm-svn: 286578
* [SelectionDAG] Add support for vector demandedelts in UDIV opcodesSimon Pilgrim2016-11-111-2/+4
| | | | llvm-svn: 286576
* [DAG Combiner] Fix the native computation of the Newton series for reciprocalsEvandro Menezes2016-11-101-28/+30
| | | | | | | | | | | | The generic infrastructure to compute the Newton series for reciprocal and reciprocal square root was conceived to allow a target to compute the series itself. However, the original code did not properly consider this condition if returned by a target. This patch addresses the issues to allow a target to compute the series on its own. Differential revision: https://reviews.llvm.org/D22975 llvm-svn: 286523
* [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodesSimon Pilgrim2016-11-101-3/+6
| | | | llvm-svn: 286516
* [SelectionDAG] Add support for splatted vectors in SUB opcodeSimon Pilgrim2016-11-101-1/+1
| | | | llvm-svn: 286509
* [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodesSimon Pilgrim2016-11-101-1/+2
| | | | llvm-svn: 286481
* Use common SDLoc. NFCI.Simon Pilgrim2016-11-101-3/+3
| | | | llvm-svn: 286473
* [SelectionDAG] Add support for vector demandedelts in MUL opcodesSimon Pilgrim2016-11-101-3/+5
| | | | llvm-svn: 286471
* [SelectionDAG] Add support for vector demandedelts in SRA opcodesSimon Pilgrim2016-11-101-1/+2
| | | | llvm-svn: 286461
* [DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodesSimon Pilgrim2016-11-101-3/+2
| | | | | | | | We were failing to extract a constant splat shift value if the shifted value was being masked. The (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV) combine was unnecessarily preventing this. llvm-svn: 286454
* [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodesSimon Pilgrim2016-11-101-2/+4
| | | | llvm-svn: 286448
* [TargetLowering] Fix undef vector element issue with true/false result handlingSimon Pilgrim2016-11-081-10/+10
| | | | | | | | | | | | | | Fixed an issue with vector usage of TargetLowering::isConstTrueVal / TargetLowering::isConstFalseVal boolean result matching. The comment said we shouldn't handle constant splat vectors with undef elements. But the the actual code was returning false if the build vector contained no undef elements.... This patch now ignores the number of undefs (getConstantSplatNode will return null if the build vector is all undefs). The change has also unearthed a couple of missed opportunities in AVX512 comparison code that will need to be addressed. Differential Revision: https://reviews.llvm.org/D26031 llvm-svn: 286238
* [VectorLegalizer] Expansion of CTLZ using CTPOP when possibleSimon Pilgrim2016-11-081-6/+50
| | | | | | | | | | This patch avoids scalarization of CTLZ by instead expanding to use CTPOP (ref: "Hacker's Delight") when the necessary operations are available. This also adds the necessary cost models for X86 SSE2 targets (the main beneficiary) to ensure vectorization only happens when its useful. Differential Revision: https://reviews.llvm.org/D25910 llvm-svn: 286233
* Add -O0 support for @llvm.invariant.group.barrier by discarding it if it ↵Richard Smith2016-11-072-0/+2
| | | | | | | | gets to ISel. Differential Revision: https://reviews.llvm.org/D26292 llvm-svn: 286119
* [SelectionDAG] Add support for vector demandedelts in XOR opcodesSimon Pilgrim2016-11-061-2/+4
| | | | llvm-svn: 286075
* [SelectionDAG] Add support for vector demandedelts in OR opcodesSimon Pilgrim2016-11-061-2/+4
| | | | llvm-svn: 286071
* DAGCombiner: fix use-after-free when merging consecutive storesNicolai Haehnle2016-11-031-18/+22
| | | | | | | | | | | | | | | Summary: Have MergeConsecutiveStores explicitly return information about the stores that were merged, so that we can safely determine whether the starting node has been freed. Reviewers: chandlerc, bogner, niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25601 llvm-svn: 285916
* Expandload and Compressstore intrinsicsElena Demikhovsky2016-11-034-22/+72
| | | | | | | | 2 new intrinsics covering AVX-512 compress/expand functionality. This implementation includes syntax, DAG builder, operation lowering and tests. Does not include: handling of illegal data types, codegen prepare pass and the cost model. llvm-svn: 285876
* Use !operator to test if APInt is zero/non-zero. NFCI.Simon Pilgrim2016-11-021-3/+3
| | | | | | Avoids APInt construction and slower comparisons. llvm-svn: 285822
* Simplify.Joerg Sonnenberger2016-11-021-2/+2
| | | | llvm-svn: 285802
* [DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded ↵Sanjay Patel2016-10-311-7/+18
| | | | | | | | | | | | | | | | bits (PR30841) This bug was exposed by using nsw/nuw for more aggressive folds in: https://reviews.llvm.org/rL284844 The changes mimic the IR demanded bits logic in InstCombiner::SimplifyDemandedUseBits(), but we can't just flip flag bits in the DAG; we have to create a new node that has the bits cleared. This should fix: https://llvm.org/bugs/show_bug.cgi?id=30841 llvm-svn: 285656
* [DAG] x | x --> xSanjay Patel2016-10-301-0/+4
| | | | llvm-svn: 285522
* [DAG] x & x --> xSanjay Patel2016-10-301-0/+4
| | | | llvm-svn: 285521
* [DAGCombiner] (REAPPLIED) Add vector demanded elements support to ↵Simon Pilgrim2016-10-291-13/+111
| | | | | | | | | | | | | | | | | | | | computeKnownBits Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander! Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285494
* [DAGCombiner] Fix a crash visiting `AND` nodes.Davide Italiano2016-10-281-1/+6
| | | | | | | | | | Instead of asserting that the shift count is != 0 we just bail out as it's not profitable trying to optimize a node which will be removed anyway. Differential Revision: https://reviews.llvm.org/D26098 llvm-svn: 285480
* SDAG: Make sure we use an allocatable reg class when we create this vregJustin Bogner2016-10-281-0/+2
| | | | | | | As per the discussion on r280783, if constrainRegClass fails we need to call getAllocatableClass like we did before that commit. llvm-svn: 285467
* [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has ↵Simon Pilgrim2016-10-281-0/+4
| | | | | | | | no known bits No need to check the remaining elements - no common known bits are available. llvm-svn: 285399
* [SelectionDAG] Tidyup UDIV computeKnownBits implementationSimon Pilgrim2016-10-281-2/+0
| | | | | | No need to clear KnownOne2/KnownZero2 bits as the next call to computeKnownBits will overwrite them anyway llvm-svn: 285398
* [SelectionDAG] Increment computeKnownBits recursion depth for ↵Simon Pilgrim2016-10-281-2/+2
| | | | | | SMIN/SMAX/UMIN/UMAX like all other ops llvm-svn: 285397
* Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits"Juergen Ributzka2016-10-281-111/+13
| | | | | | | This seems to have increased LTO compile time bejond 2x of previous builds. See http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto/10676/ llvm-svn: 285381
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsSimon Pilgrim2016-10-271-13/+111
| | | | | | | | | | | | | | | | Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285296
* Do not assume that FP vector operands are never legalized by expandingNemanja Ivanovic2016-10-261-1/+2
| | | | | | | | | | | This patch ensures that if a floating point vector operand is legalized by expanding, it is legalized through the stack rather than by calling DAGTypeLegalizer::IntegerToVector which will cause a failure since the operand is a non-integer type. This fixes PR 30715. llvm-svn: 285231
* LegalizeDAG: Support promoting [US]DIV and [US]REM operationsTom Stellard2016-10-261-1/+18
| | | | | | | | | | | | | | | | | | Summary: AMDGPU will need this one i16 is added as a legal type. This is tested by: test/CodeGen/AMDGPU/sdiv.ll test/CodeGen/AMDGPU/sdivrem24.ll test/CodeGen/AMDGPU/udiv.ll test/CodeGen/AMDGPU/udivrem24.ll Reviewers: bogner, efriedma Subscribers: efriedma, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D25699 llvm-svn: 285199
* [DAGCombiner] Enable (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), ↵Simon Pilgrim2016-10-251-3/+3
| | | | | | -1)) combine for splatted vectors llvm-svn: 285129
* [DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
| | | | | | SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927 llvm-svn: 285123
* [DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
| | | | | | SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927 llvm-svn: 285118
* Switch lowering: improve partitioning of jump tablesEvandro Menezes2016-10-251-14/+31
| | | | | | | | | | | When there's a tie between partitionings of jump tables, consider also cases that result in no jump tables, but in one or a few cases. The motivation is that many contemporary processors typically perform case switches fairly quickly. Differential revision: https://reviews.llvm.org/D25212 llvm-svn: 285099
* [DAGCombine] Preserve shuffles when one of the vector operands is constantZvi Rackover2016-10-251-34/+75
| | | | | | | | | | | | | | | | | | | | Summary: Do *not* perform combines such as: vector_shuffle<4,1,2,3>(build_vector(Ud, C0, C1 C2), scalar_to_vector(X)) -> build_vector(X, C0, C1, C2) Keeping the shuffle allows lowering the constant build_vector to a materialized constant vector (such as a vector-load from the constant-pool or some other idiom). Reviewers: delena, igorb, spatel, mkuper, andreadb, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25524 llvm-svn: 285063
* [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar ↵Simon Pilgrim2016-10-241-6/+7
| | | | | | | | | | or vector splats Use isConstOrConstSplat helper. Also use APInt instead of getZExtValue directly to avoid out of range issues. llvm-svn: 285033
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