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* Clean up the atomic opcodes in SelectionDAG.Dan Gohman2008-12-234-536/+138
| | | | | | | | | | | | | This removes all the _8, _16, _32, and _64 opcodes and replaces each group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode is now used to carry the size information. In tablegen, the size-specific opcodes are replaced by size-independent opcodes that utilize the ability to compose them with predicates. This shrinks the per-opcode tables and makes the code that handles atomics much more concise. llvm-svn: 61389
* Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman2008-12-234-10/+20
| | | | | | code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions. llvm-svn: 61376
* Avoid an unnecessary call to allnodes_size(), which is linear.Dan Gohman2008-12-231-8/+11
| | | | llvm-svn: 61372
* One more permutation of subtracting off a base value.Dale Johannesen2008-12-231-0/+6
| | | | llvm-svn: 61361
* Added support for vector widening.Mon P Wang2008-12-186-43/+1238
| | | | llvm-svn: 61209
* Fix expansion of vsetcc to set the high bit for true instead of 1.Mon P Wang2008-12-171-4/+6
| | | | llvm-svn: 61129
* Double the amount of memory reserved for SUnits. This is aDan Gohman2008-12-171-1/+3
| | | | | | | | | temporary workaround for an obscure bug. When node cloning is used, it is possible that more SUnits will be created, and if the SUnits std::vector has to reallocate, it will invalidate all the graph edges. llvm-svn: 61122
* Fix for PR3225: disable a broken optimization inEli Friedman2008-12-171-0/+3
| | | | | | | | | DAGTypeLegalizer::ExpandShiftWithKnownAmountBit. In terms of restoring the optimization, the best fix here isn't obvious... any ideas? llvm-svn: 61119
* A new dag combine; several permutations of thisDale Johannesen2008-12-161-0/+6
| | | | | | are there under ADD, this one was missing. llvm-svn: 61107
* Preserve SourceValue information when lowering produces multiple loads fromDan Gohman2008-12-161-3/+6
| | | | | | different offsets within the same stack slot. llvm-svn: 61093
* We have decided not to support inline asm where an output operand with a ↵Evan Cheng2008-12-161-11/+12
| | | | | | matching input operand with incompatible type (i.e. either one is a floating point and the other is an integer or the sizes of the types differ). SelectionDAGBuild will catch these and exit with an error. llvm-svn: 61092
* Remove some special-case logic in ScheduleDAGSDNodes's Dan Gohman2008-12-161-10/+0
| | | | | | | latency computation code that is no longer needed with the new method for handling latencies. llvm-svn: 61074
* Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman2008-12-164-57/+49
| | | | | | | | | | | | | | computation code. Also, avoid adding output-depenency edges when both defs are dead, which frequently happens with EFLAGS defs. Compute Depth and Height lazily, and always in terms of edge latency values. For the schedulers that don't care about latency, edge latencies are set to 1. Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array. These are all subsumed by the Depth and Height fields. llvm-svn: 61073
* Make addPred and removePred return void, since the return value is notDan Gohman2008-12-162-8/+8
| | | | | | currently used by anything. llvm-svn: 61066
* Added support for splitting and scalarizing vector shifts.Mon P Wang2008-12-152-0/+19
| | | | llvm-svn: 61050
* Fix printing of PseudoSourceValues in SDNode graphs.Dan Gohman2008-12-151-5/+3
| | | | llvm-svn: 61036
* Added support to LegalizeType for expanding the operands of scalar to vectorMon P Wang2008-12-153-9/+57
| | | | | | | and insert vector element. Modified extract vector element to extend the result to match the expected promoted type. llvm-svn: 61029
* Reapply r60997, this time without forgetting thatDuncan Sands2008-12-142-7/+14
| | | | | | | target constants are allowed to have an illegal type. llvm-svn: 61006
* Temporarily revert r60997. It was causing this failure:Bill Wendling2008-12-132-10/+7
| | | | | | | | | | | | | | | | | | | Running /Users/void/llvm/llvm.src/test/CodeGen/Generic/dg.exp ... FAIL: /Users/void/llvm/llvm.src/test/CodeGen/Generic/asm-large-immediate.ll Failed with exit(1) at line 1 while running: llvm-as < /Users/void/llvm/llvm.src/test/CodeGen/Generic/asm-large-immediate.ll | llc | /usr/bin/grep 68719476738 Assertion failed: ((TypesNeedLegalizing || getTypeAction(VT) == Legal) && "Illegal type introduced after type legalization?"), function HandleOp, file /Users/void/llvm/llvm.src/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp, line 493. 0 llc 0x0085392e char const* std::find<char const*, char>(char const*, char const*, char const&) + 98 1 llc 0x00853e63 llvm::sys::PrintStackTraceOnErrorSignal() + 593 2 libSystem.B.dylib 0x96cac09b _sigtramp + 43 3 libSystem.B.dylib 0xffffffff _sigtramp + 1765097359 4 libSystem.B.dylib 0x96d24ec2 raise + 26 5 libSystem.B.dylib 0x96d3447f abort + 73 6 libSystem.B.dylib 0x96d26063 __assert_rtn + 101 7 llc 0x004f9018 llvm::cast_retty<llvm::SubprogramDesc, llvm::DebugInfoDesc*>::ret_type llvm::cast<llvm::Sub ... llvm-svn: 61001
* LegalizeDAG is not supposed to introduce illegalDuncan Sands2008-12-132-7/+10
| | | | | | | types into the DAG if they were not already there. Check this with an assertion. llvm-svn: 60997
* Remove assertion to allow promotion of a truncating store operandMon P Wang2008-12-131-2/+0
| | | | llvm-svn: 60975
* Added basic support for expanding VSETCCMon P Wang2008-12-131-2/+21
| | | | llvm-svn: 60974
* On big-endian machines it is wrong to do a fullDuncan Sands2008-12-131-19/+22
| | | | | | | | | | width register load followed by a truncating store for the copy, since the load will not place the value in the lower bits. Probably partial loads/stores can never happen here, but fix it anyway. llvm-svn: 60972
* When expanding unaligned loads and stores do not makeDuncan Sands2008-12-121-34/+123
| | | | | | | | | | | | | | | | | | | | | | | | use of illegal integer types: instead, use a stack slot and copying via integer registers. The existing code is still used if the bitconvert is to a legal integer type. This fires on the PPC testcases 2007-09-08-unaligned.ll and vec_misaligned.ll. It looks like equivalent code is generated with these changes, just permuted, but it's hard to tell. With these changes, nothing in LegalizeDAG produces illegal integer types anymore. This is a prerequisite for removing the LegalizeDAG type legalization code. While there I noticed that the existing code doesn't handle trunc store of f64 to f32: it turns this into an i64 store, which represents a 4 byte stack smash. I added a FIXME about this. Hopefully someone more motivated than I am will take care of it. llvm-svn: 60964
* Fix add/sub expansion: don't create ADD / SUB with two results (seems like ↵Evan Cheng2008-12-121-5/+5
| | | | | | everyone is doing this these days :-). Patch by Daniel M Gessel! llvm-svn: 60958
* When using a 4 byte jump table on a 64 bit machine,Duncan Sands2008-12-121-11/+3
| | | | | | | | do an extending load of the 4 bytes rather than a potentially illegal (type) i32 load followed by a sign extend. llvm-svn: 60945
* Added support for SELECT v8i8 v4i16 for X86 (MMX)Mon P Wang2008-12-121-0/+4
| | | | | | Added support for TRUNC v8i16 to v8i8 for X86 (MMX) llvm-svn: 60916
* Redo the arithmetic with overflow architecture. I was changing the semantics ofBill Wendling2008-12-121-15/+0
| | | | | | | | | | | | ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
* Avoid generating a convert_rndsat node when the src and dest type are the same.Mon P Wang2008-12-111-0/+4
| | | | llvm-svn: 60869
* Clarify FIXME.Bill Wendling2008-12-111-6/+6
| | | | llvm-svn: 60867
* Whitespace clean up (tabs with spaces)Mon P Wang2008-12-111-8/+8
| | | | llvm-svn: 60866
* Make fix for r60829 less conservative to allow the proper optimization forMon P Wang2008-12-111-2/+9
| | | | | | vec_extract-sse4.ll. llvm-svn: 60865
* If ADD, SUB, or MUL have an overflow bit that's used, don't do transformation onBill Wendling2008-12-101-0/+15
| | | | | | | them. The DAG combiner expects that nodes that are transformed have one value result. llvm-svn: 60857
* For amusement, implement SADDO, SSUBO, UADDO, USUBODuncan Sands2008-12-102-19/+80
| | | | | | | | | for promoted integer types, eg: i16 on ppc-32, or i24 on any platform. Complete support for arbitrary precision integers would require handling expanded integer types, eg: i128, but I couldn't be bothered. llvm-svn: 60834
* Fixed a bug when trying to optimize a extract vector element of aMon P Wang2008-12-101-1/+2
| | | | | | bit convert that changes the number of elements of a shuffle. llvm-svn: 60829
* Whitespace changes.Bill Wendling2008-12-101-1/+1
| | | | llvm-svn: 60826
* Whitespace fixes.Bill Wendling2008-12-101-14/+12
| | | | llvm-svn: 60818
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-094-221/+232
| | | | | | | | | | | | | | | | | The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. llvm-svn: 60806
* Add sub/mul overflow intrinsics. This currently doesn't have aBill Wendling2008-12-096-25/+87
| | | | | | | target-independent way of determining overflow on multiplication. It's very tricky. Patch by Zoltan Varga! llvm-svn: 60800
* Fix PR3117: not all nodes being legalized. TheDuncan Sands2008-12-097-207/+467
| | | | | | | | | | | | | | | | | | | | | | | essential problem was that the DAG can contain random unused nodes which were never analyzed. When remapping a value of a node being processed, such a node may become used and need to be analyzed; however due to operands being transformed during analysis the node may morph into a different one. Users of the morphing node need to be updated, and this wasn't happening. While there I added a bunch of documentation and sanity checks, so I (or some other poor soul) won't have to scratch their head over this stuff so long trying to remember how it was all supposed to work next time some obscure problem pops up! The extra sanity checking exposed a few places where invariants weren't being preserved, so those are fixed too. Since some of the sanity checking is expensive, I added a flag to turn it on. It is also turned on when building with ENABLE_EXPENSIVE_CHECKS=1. llvm-svn: 60797
* In LegalizeOp, don't change the result type of CONVERT_RNDSAT when promotingMon P Wang2008-12-091-2/+2
| | | | | | one of its operand. llvm-svn: 60749
* Fix getNode to allow a vector for the shift amount for shifts of vectors.Mon P Wang2008-12-092-9/+33
| | | | | | | | Fix the shift amount when unrolling a vector shift into scalar shifts. Fix problem in getShuffleScalarElt where it assumes that the input of a bit convert must be a vector. llvm-svn: 60740
* Factor out the code for sign-extending/truncating gep indicesDan Gohman2008-12-081-23/+32
| | | | | | | | | and use it in x86 address mode folding. Also, make getRegForValue return 0 for illegal types even if it has a ValueMap for them, because Argument values are put in the ValueMap. This fixes PR3181. llvm-svn: 60696
* When allocating a stack temporary, use the correctDuncan Sands2008-12-041-1/+1
| | | | | | | number of bytes for types such as i1 which are not a multiple of 8 bits in length. llvm-svn: 60543
* Make debug output more informative.Dan Gohman2008-12-041-1/+1
| | | | llvm-svn: 60524
* Only check that the result of the mapping was notDuncan Sands2008-12-031-0/+1
| | | | | | a new node if the node was actually remapped. llvm-svn: 60482
* Remove a (what appears to be) overly strict assertion. Here is what happened:Evan Cheng2008-12-021-1/+0
| | | | | | | | | | | 1. ppcf128 select is expanded to f64 select's. 2. f64 select operand 0 is an i1 truncate, it's promoted to i32 zero_extend. 3. f64 select is updated. It's changed back to a "NewNode" and being re-analyzed. 4. f64 select operands are being processed. Operand 0 is a "NewNode". It's being expunged out of ReplacedValues map. 5. ExpungeNode tries to remap f64 select and notice it's a "NewNode" and assert. Duncan, please take a look. Thanks. llvm-svn: 60443
* Non-functional change: make custom lowering for truncate stylisticallyScott Michel2008-12-021-5/+12
| | | | | | consistent with the way it's generally done in other places. llvm-svn: 60439
* One more transformation.Dale Johannesen2008-12-021-0/+8
| | | | llvm-svn: 60432
* make it possible to custom lower TRUNCATE (needed for the CellSPU target)Tilmann Scheller2008-12-021-0/+5
| | | | llvm-svn: 60409
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