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* when transforming a MULHS into a wider MUL, there is no need to SRA theChris Lattner2010-12-151-1/+1
| | | | | | result, the top bits are truncated off anyway, just use SRL. llvm-svn: 121846
* Add a couple dag combines to transform mulhi/mullo into a wider multiplyChris Lattner2010-12-131-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
* reduce indentation by using continue, no functionality change.Chris Lattner2010-12-131-38/+41
| | | | llvm-svn: 121662
* Catch attempts to remove a deleted node from the CSE maps. Better toDuncan Sands2010-12-121-3/+2
| | | | | | | catch this here rather than later after accessing uninitialized memory etc. Fires when compiling the testcase in PR8237. llvm-svn: 121635
* Initial support for nested CALLSEQ_START/CALLSEQ_END constructs in LegalizeDAG.Stuart Hastings2010-12-091-8/+24
| | | | | | Necessary for byval support on ARM. Radar 7662569. llvm-svn: 121412
* 80-col fixups.Eric Christopher2010-12-091-9/+15
| | | | llvm-svn: 121356
* Reword comment slightly.Eric Christopher2010-12-081-1/+1
| | | | llvm-svn: 121293
* PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad2010-12-076-69/+59
| | | | | | | | zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG ↵Devang Patel2010-12-062-23/+14
| | | | | | message instead of creating DBG_VALUE for undefined value in reg0. llvm-svn: 121059
* Remove unneeded zero arrays.Benjamin Kramer2010-12-042-4/+2
| | | | llvm-svn: 120910
* PR5207: Rename overloaded APInt methods set(), clear(), flip() toJay Foad2010-12-013-7/+7
| | | | | | setAllBits(), setBit(unsigned), etc. llvm-svn: 120564
* Enable sibling call optimization of libcalls which are expanded duringEvan Cheng2010-11-301-6/+17
| | | | | | | | | | | legalization time. Since at legalization time there is no mapping from SDNode back to the corresponding LLVM instruction and the return SDNode is target specific, this requires a target hook to check for eligibility. Only x86 and ARM support this form of sibcall optimization right now. rdar://8707777 llvm-svn: 120501
* add TLI support indicating that jumps are more expensive than logical operationsChris Lattner2010-11-302-1/+4
| | | | | | and use this to disable a specific optimization. Patch by Micah Villmow! llvm-svn: 120435
* PR5207: Make APInt::set(), APInt::clear() and APInt::flip() return void.Jay Foad2010-11-301-2/+3
| | | | llvm-svn: 120413
* Merge System into Support.Michael J. Spencer2010-11-292-2/+2
| | | | llvm-svn: 120298
* Fix a comment typo.Bob Wilson2010-11-281-1/+1
| | | | llvm-svn: 120235
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-2313-518/+516
| | | | llvm-svn: 119990
* Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization.Benjamin Kramer2010-11-221-1/+47
| | | | | | | This currently only catches the most basic case, a two-case switch, but can be extended later. llvm-svn: 119964
* Silence Release build warnings about unused functions.Benjamin Kramer2010-11-201-0/+2
| | | | llvm-svn: 119903
* On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics,Duncan Sands2010-11-201-9/+46
| | | | | | | | | | | so don't claim they are. They are allocated using DAG.getNode, so attempts to access MemSDNode fields results in reading off the end of the allocated memory. This fixes crashes with "llc -debug" due to debug code trying to print MemSDNode fields for these barrier nodes (since the crashes are not deterministic, use valgrind to see this). Add some nasty checking to try to catch this kind of thing in the future. llvm-svn: 119901
* Removing the useless test that I added recently. It was meant as an example, ↵Andrew Trick2010-11-201-3/+6
| | | | | | but not complicated enough to merit another test. llvm-svn: 119898
* Check for _setjmp too, because it's also used.Bill Wendling2010-11-201-0/+1
| | | | llvm-svn: 119875
* Make isScalarToVector to return false if the node is a scalar. This will preventMon P Wang2010-11-191-0/+2
| | | | | | | DAGCombine from making an illegal transformation of bitcast of a scalar to a vector into a scalar_to_vector. llvm-svn: 119819
* Fix thinko: we must turn select(anyext, sext) into sext(select)Duncan Sands2010-11-181-1/+2
| | | | | | not anyext(select). Spotted by Frits van Bommel. llvm-svn: 119739
* The DAGCombiner was threading select over pairs of extending loads evenDuncan Sands2010-11-181-0/+5
| | | | | | | | | | if the extension types were not the same. The result was that if you fed a select with sext and zext loads, as in the testcase, then it would get turned into a zext (or sext) of the select, which is wrong in the cases when it should have been an sext (resp. zext). Reported and diagnosed by Sebastien Deldon. llvm-svn: 119728
* Do not throw away alignment when generating the DAG forDale Johannesen2010-11-181-1/+1
| | | | | | | | memset; we may need it to decide between MOVAPS and MOVUPS later. Adjust a test that was looking for wrong code. PR 3866 / 8675131. llvm-svn: 119605
* Bug 8621 fix - pointer cast stripped from inline asm constraint argument.John Thompson2010-11-171-3/+0
| | | | llvm-svn: 119590
* Split pseudo-instruction expansion into a separate pass, to make itDan Gohman2010-11-161-13/+0
| | | | | | | easier to debug, and to avoid complications when the CFG changes in the middle of the instruction selection process. llvm-svn: 119382
* typo (4th checkin for one fix)Andrew Trick2010-11-121-1/+1
| | | | llvm-svn: 118913
* Fixes PR8287: SD scheduling time. The fix is a failsafe that preventsAndrew Trick2010-11-121-13/+53
| | | | | | | | | catastrophic compilation time in the event of unreasonable LLVM IR. Code quality is a separate issue--someone upstream needs to do a better job of reducing to llvm.memcpy. If the situation can be reproduced with any supported frontend, then it will be a separate bug. llvm-svn: 118904
* tidy up.Chris Lattner2010-11-121-7/+5
| | | | llvm-svn: 118896
* Remove the memmove->memcpy optimization from CodeGen. MemCpyOpt does this.Dan Gohman2010-11-111-14/+0
| | | | llvm-svn: 118789
* Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shlDan Gohman2010-11-091-0/+1
| | | | | | in order to fold it into a load. llvm-svn: 118471
* Fix an inline asm pasto from 117667; was preventingDale Johannesen2010-11-091-1/+2
| | | | | | {i64, i64} from matching i128. llvm-svn: 118465
* When passing a parameter using the 'byval' mechanism, inline code needs to ↵Duncan Sands2010-11-051-0/+2
| | | | | | | | | | | | | be used to perform the copy, which may be of lots of memory [*]. It would be good if the fall-back code generated something reasonable, i.e. did the copy in a loop, rather than vast numbers of loads and stores. Add a note about this. Currently target specific code seems to always kick in so this is more of a theoretical issue rather than a practical one now that X86 has been fixed. [*] It's amazing how often people pass mega-byte long arrays by copy... llvm-svn: 118275
* Just return undef for invalid masks or elts, and since we're doing that,Eric Christopher2010-11-031-5/+6
| | | | | | just do it earlier too. llvm-svn: 118195
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-032-7/+5
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-3/+3
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* If we have an undef mask our Elt will be -1 for our access, handleEric Christopher2010-11-031-3/+7
| | | | | | | | this by using an undef as a pointer. Fixes rdar://8625016 llvm-svn: 118164
* Fix DAGCombiner to avoid going into an infinite loop when itDan Gohman2010-11-031-1/+36
| | | | | | | encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff). This fixes rdar://8606584. llvm-svn: 118143
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-032-4/+15
| | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 llvm-svn: 118135
* If value map does not have register for an argument then try to find frame ↵Devang Patel2010-11-021-5/+8
| | | | | | index before giving up. llvm-svn: 118022
* Use frameindex, if available, as a last resort to emit debug info for a ↵Devang Patel2010-11-021-2/+13
| | | | | | parameter. llvm-svn: 118020
* Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson2010-10-291-5/+0
| | | | llvm-svn: 117720
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-292-24/+78
| | | | | | | | | | | | | | | | | | | | | | | | | operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-292-46/+76
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson2010-10-281-24/+28
| | | | | | Also do some minor refactoring to reduce indentation. llvm-svn: 117558
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-281-0/+3
| | | | llvm-svn: 117531
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng2010-10-281-3/+0
| | | | | | to fail. Ugh. llvm-svn: 117520
* Fix a major bug in operand latency computation. The use index must be adjustedEvan Cheng2010-10-281-0/+3
| | | | | | by the number of defs first for it to match the instruction itinerary. llvm-svn: 117518
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