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* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-287-75/+75
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel2011-06-272-0/+24
| | | | | | at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. llvm-svn: 133953
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-272-4/+4
| | | | llvm-svn: 133944
* The index stored in the RegDefIter is one after the current index. When ↵Owen Anderson2011-06-271-1/+1
| | | | | | getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped. llvm-svn: 133923
* pre-RA-sched: Cleanup register pressure tracking.Andrew Trick2011-06-272-16/+4
| | | | | | | | Removed the check that peeks past EXTRA_SUBREG, which I don't think makes sense any more. Intead treat it as a normal register def. No significant affect on x86 or ARM benchmarks. llvm-svn: 133917
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-274-4/+6
| | | | | | | | | | | | | | | | | | | | | | Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. llvm-svn: 133902
* The scheduler needs to be aware on the existence of untyped nodes when it ↵Owen Anderson2011-06-241-1/+2
| | | | | | performs type propagation for EXTRACT_SUBREG. llvm-svn: 133838
* Handle debug info for i128 constants.Devang Patel2011-06-242-9/+10
| | | | llvm-svn: 133821
* Replace the existing forms of ConstantArray::get() with a single formJay Foad2011-06-221-1/+1
| | | | | | that takes an ArrayRef. llvm-svn: 133615
* Fix some trailing issues from my introduction of MVT::untyped and its use ↵Owen Anderson2011-06-211-1/+11
| | | | | | for REGISTER_SEQUENCE. llvm-svn: 133567
* Teach dag combine to match halfword byteswap patterns.Evan Cheng2011-06-211-2/+264
| | | | | | | | | | | | | | 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 llvm-svn: 133503
* Fix PromoteIntRes_TRUNCATE: Add support for cases where theNadav Rotem2011-06-201-4/+28
| | | | | | | source vector type is to be split while the target vector is to be promoted. (eg: <4 x i64> -> <4 x i8> ) llvm-svn: 133424
* Code cleanups: Remove duplicated logic in PromotInteRes_BITCAST, reserve ↵Nadav Rotem2011-06-191-7/+5
| | | | | | vector space, reuse types. llvm-svn: 133389
* Calls to AssertZext and getZeroExtendInReg must be made using scalar types.Nadav Rotem2011-06-191-3/+4
| | | | llvm-svn: 133388
* When promoting the vector elements in CopyToParts, use vector truncNadav Rotem2011-06-191-11/+3
| | | | | | instead of scalarizing, and doing an element-by-element truncat. llvm-svn: 133382
* Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.Benjamin Kramer2011-06-182-4/+4
| | | | llvm-svn: 133348
* Remove unused but set variables.Benjamin Kramer2011-06-182-19/+4
| | | | llvm-svn: 133347
* Fix UMULO support for 2x register width to allow the fullEric Christopher2011-06-181-0/+21
| | | | | | | | | range without a libcall to a new mulo<mode> libcall that we'd have to create. Finishes the rest of rdar://9090077 and rdar://9210061 llvm-svn: 133318
* Fix comment.Eric Christopher2011-06-171-2/+1
| | | | llvm-svn: 133307
* Lower multiply with overflow checking to __mulo<mode>Eric Christopher2011-06-173-4/+71
| | | | | | | | | calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-161-2/+7
| | | | | | | | | | In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> llvm-svn: 133210
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-163-11/+50
| | | | | | | | BranchProbabilityInfo (expect setEdgeWeight which is not available here). Branch Weights are kept in MachineBasicBlocks. To turn off this analysis set -use-mbpi=false. llvm-svn: 133184
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its ↵Owen Anderson2011-06-161-5/+6
| | | | | | | | first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change. This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. llvm-svn: 133178
* Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen2011-06-161-9/+16
| | | | | | | | | | | | | This virtual function will replace allocation_order_begin/end as the one to override when implementing custom allocation orders. It is simpler to have one function return an ArrayRef than having two virtual functions computing different ends of the same array. Use getRawAllocationOrder() in place of allocation_order_begin() where it makes sense, but leave some clients that look like they really want the filtered allocation orders from RegisterClassInfo. llvm-svn: 133170
* Add a DAGCombine for (ext (binop (load x), cst)).Nick Lewycky2011-06-161-61/+109
| | | | llvm-svn: 133124
* Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson2011-06-152-9/+47
| | | | | | features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. llvm-svn: 133106
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-152-15/+43
| | | | | | Added a test case for handling physreg aliases during pre-RA-sched. llvm-svn: 133063
* getZeroExtendInReg needs to get a scalar typeNadav Rotem2011-06-151-1/+2
| | | | llvm-svn: 133057
* Enable the simplification of truncating-store after fixing the usage ofNadav Rotem2011-06-152-4/+5
| | | | | | | | GetDemandBits (which must operate on the vector element type). Fix the a usage of getZeroExtendInReg which must also be done on scalar types. llvm-svn: 133052
* When pattern matching during instruction selection make sure shl x,1 is notChad Rosier2011-06-141-0/+3
| | | | | | | | converted to add x,x if x is a undef. add undef, undef does not guarantee that the resulting low order bit is zero. Fixes <rdar://problem/9453156> and <rdar://problem/9487392>. llvm-svn: 133022
* Add a testcase for checking the integer-promotion of many different vectorNadav Rotem2011-06-142-2/+171
| | | | | | | | | | | | | types (with power of two types such as 8,16,32 .. 512). Fix a bug in the integer promotion of bitcast nodes. Enable integer expanding only if the target of the conversion is an integer (when the type action is scalarize). Add handling to the legalization of vector load/store in cases where the saved vector is integer-promoted. llvm-svn: 132985
* Disable trunc-store simplification on vectors.Nadav Rotem2011-06-141-1/+1
| | | | llvm-svn: 132984
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-141-2/+3
| | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
* Fix a bug in FindMemType. When widening vector loads, use a wider memory typeNadav Rotem2011-06-131-0/+2
| | | | | | | only if the number of packed elements is a power of two. Bug found in Duncan's testcase. llvm-svn: 132923
* Fix a bug in the calculation of the vectorTypeBreakdown into registers. OddNadav Rotem2011-06-121-5/+17
| | | | | | types such as i33 were rounded to i32. Originated from Duncan's testcase. llvm-svn: 132893
* Improve the generated code by getCopyFromPartsVector for promoted integer types.Nadav Rotem2011-06-121-21/+20
| | | | | | | | | Instead of scalarizing, and doing an element-by-element truncat, use vector truncate. Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's testcase). llvm-svn: 132892
* Revert r132871.Chad Rosier2011-06-111-1/+1
| | | | llvm-svn: 132872
* Typo.Chad Rosier2011-06-111-1/+1
| | | | llvm-svn: 132871
* 80-col cleanups.Eric Christopher2011-06-101-6/+5
| | | | llvm-svn: 132863
* Change this DAGCombine to build AND of SHR instead of SHR of AND; this ↵Eli Friedman2011-06-091-15/+16
| | | | | | | | matches the ordering we prefer in instcombine. Part of rdar://9562809. The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now. llvm-svn: 132809
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-082-8/+11
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick2011-06-081-1/+0
| | | | llvm-svn: 132751
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
| | | | | | | I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. llvm-svn: 132701
* Add methods to support the integer-promotion of vector types. Methods toNadav Rotem2011-06-063-0/+192
| | | | | | legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. llvm-svn: 132689
* Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings2011-06-061-6/+8
| | | | llvm-svn: 132681
* PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman2011-06-061-1/+3
| | | | llvm-svn: 132676
* TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem2011-06-041-2/+40
| | | | | | (copyFromParts/copyToParts). llvm-svn: 132649
* TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem2011-06-041-16/+22
| | | | | | | | | (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
* Add a TODO about memory operands.Eric Christopher2011-06-031-1/+5
| | | | llvm-svn: 132559
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-022-3/+7
| | | | | | Part of rdar://9119939 llvm-svn: 132510
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