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* [DAGCombine] Avoid INSERT_SUBVECTOR reinsertions (PR28678)Simon Pilgrim2016-08-101-1/+10
| | | | | | | | | | | If the input vector to INSERT_SUBVECTOR is another INSERT_SUBVECTOR, and this inserted subvector replaces the last insertion, then insert into the common source vector. i.e. INSERT_SUBVECTOR( INSERT_SUBVECTOR( Vec, SubOld, Idx ), SubNew, Idx ) --> INSERT_SUBVECTOR( Vec, SubNew, Idx ) Differential Revision: https://reviews.llvm.org/D23330 llvm-svn: 278211
* [DAGCombiner] Better support for shifting large value type by constantsSimon Pilgrim2016-08-091-17/+42
| | | | | | | | | | As detailed on D22726, much of the shift combining code assume constant values will fit into a uint64_t value and calls ConstantSDNode::getZExtValue where it probably shouldn't (leading to asserts). Using APInt directly avoids this problem but we encounter other assertions if we attempt to compare/operate on 2 APInt of different bitwidths. This patch adds a helper function to ensure that 2 APInt values are zero extended as required so that they can be safely used together. I've only added an initial example use for this to the '(SHIFT (SHIFT x, c1), c2) --> (SHIFT x, (ADD c1, c2))' combines. Further cases can easily be added as required. Differential Revision: https://reviews.llvm.org/D23007 llvm-svn: 278141
* [SelectionDAG] Refactor visitInlineAsm a bit. NFCI.Diana Picus2016-08-081-151/+198
| | | | | | This shaves off ~100 lines from visitInlineAsm. llvm-svn: 277987
* [X86] Heuristic to selectively build Newton-Raphson SQRT estimationNikolai Bozhenov2016-08-041-2/+6
| | | | | | | | | | | | | | | | | | | | | On modern Intel processors hardware SQRT in many cases is faster than RSQRT followed by Newton-Raphson refinement. The patch introduces a simple heuristic to choose between hardware SQRT instruction and Newton-Raphson software estimation. The patch treats scalars and vectors differently. The heuristic is that for scalars the compiler should optimize for latency while for vectors it should optimize for throughput. It is based on the assumption that throughput bound code is likely to be vectorized. Basically, the patch disables scalar NR for big cores and disables NR completely for Skylake. Firstly, scalar SQRT has shorter latency than NR code in big cores. Secondly, vector SQRT has been greatly improved in Skylake and has better throughput compared to NR. Differential Revision: https://reviews.llvm.org/D21379 llvm-svn: 277725
* Typo fix in comment. NFCDiana Picus2016-08-041-1/+1
| | | | llvm-svn: 277704
* Disable shrinking of SNaN constantsElliot Colp2016-08-031-11/+17
| | | | | | | | | When expanding FP constants, we attempt to shrink doubles to floats and perform an extending load. However, on SystemZ, and possibly on other targets (I've only confirmed the problem on SystemZ), the FP extending load instruction may convert SNaN into QNaN, or may cause an exception. So in the general case, we would still like to shrink FP constants, but SNaNs should be left as doubles. Differential Revision: https://reviews.llvm.org/D22685 llvm-svn: 277602
* [DAGCombine] Make sext(setcc) combine respect getBooleanContentsMichael Kuperstein2016-08-012-9/+33
| | | | | | | | | | | We used to combine "sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)" Instead, we should combine to (select (setcc x, y, cc), T, 0) where the value of T is 1 or -1, depending on the type of the setcc, and getBooleanContents() for the type if it is not i1. This fixes PR28504. llvm-svn: 277371
* DAG: avoid duplicated truncating for sign extended operandWeiming Zhao2016-07-291-8/+10
| | | | | | | | | | | | | | | Summary: When performing cmp for EQ/NE and the operand is sign extended, we can avoid the truncaton if the bits to be tested are no less than origianl bits. Reviewers: eli.friedman Subscribers: eli.friedman, aemerson, nemanjai, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D22933 llvm-svn: 277252
* Recommitting r275284: add support to inline __builtin_mempcpyAndrew Kaylor2016-07-292-0/+48
| | | | | | | | Patch by Sunita Marathe Third try, now following fixes to MSan to handle mempcy in such a way that this commit won't break the MSan buildbots. (Thanks, Evegenii!) llvm-svn: 277189
* Cleanup TransferDbgValuesNirav Dave2016-07-291-2/+9
| | | | | | | | | | | | | | | [DAG] Check debug values for invalidation before transferring and mark old debug values invalid when transferring to another SDValue. This fixes PR28613. Reviewers: jyknight, hans, dblaikie, echristo Subscribers: yaron.keren, ismail, llvm-commits Differential Revision: https://reviews.llvm.org/D22858 llvm-svn: 277135
* Fix DbgValue handling in SelectionDAG.Nirav Dave2016-07-281-2/+3
| | | | | | | [DAG] Relocate TransferDbgValues in ReplaceAllUsesWith(SDValue, SDValue) to before we modify the CSE maps. llvm-svn: 277027
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-288-60/+59
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [DAGCombiner] Use APInt directly to detect out of range shift constantsSimon Pilgrim2016-07-271-3/+3
| | | | | | | | Using getZExtValue() will assert if the value doesn't fit into uint64_t - SHL was already doing this, I've just updated ASHR/LSHR to match As mentioned on D22726 llvm-svn: 276855
* Reverting r276771 due to MSan failures.Andrew Kaylor2016-07-272-48/+0
| | | | llvm-svn: 276824
* Re-committing r275284: add support to inline __builtin_mempcpyAndrew Kaylor2016-07-262-0/+48
| | | | | | | | Patch by Sunita Marathe Differential Revision: http://reviews.llvm.org/D21920 llvm-svn: 276771
* [SelectionDAG] Optimization of BITREVERSE legalization for power-of-2 ↵Simon Pilgrim2016-07-221-3/+46
| | | | | | | | | | | | | | integer scalar/vector types An extension of D19978, this patch replaces the default BITREVERSE evaluation of individual bit masks+shifts with block mask+shifts when we have integer elements of power-of-2 bits in size. After calling BSWAP to reverse the order of the constituent bytes (which typically follows a similar approach), every neighbouring 4-bits, 2-bits and finally 1-bit pairs are masked off and swapped over with shifts. In doing so we can significantly reduce the number of operations required. Differential Revision: https://reviews.llvm.org/D21578 llvm-svn: 276432
* [FastISel] Ignore @llvm.assume.Ahmed Bougacha2016-07-221-0/+2
| | | | llvm-svn: 276410
* AVX-512: Fixed BT instruction selection.Elena Demikhovsky2016-07-191-0/+4
| | | | | | | | | | | The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
* [X86] Accept SELECT op code for x86-64 fp128 typeChih-Hung Hsieh2016-07-181-0/+1
| | | | | | | | | | DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
* [inlineasm] Propagate operand constraints to the backendSimon Dardis2016-07-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | When SelectionDAGISel transforms a node representing an inline asm block, memory constraint information is not preserved. This can cause constraints to be broken when a memory offset is of the form: offset + frame index when the frame is resolved. By propagating the constraints all the way to the backend, targets can enforce memory operands of inline assembly to conform to their constraints. For MIPSR6, some instructions had their offsets reduced to 9 bits from 16 bits such as ll/sc. This becomes problematic when using inline assembly to perform atomic operations, as an offset can generated that is too big to encode in the instruction. Reviewers: dsanders, vkalintris Differential Review: https://reviews.llvm.org/D21615 llvm-svn: 275786
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-1512-607/+462
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-153-11/+9
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* Fix copy/paste bug in r275340.Michael Kuperstein2016-07-131-1/+1
| | | | llvm-svn: 275343
* [DAG] Correctly chain masked loadsMichael Kuperstein2016-07-131-9/+8
| | | | | | | | | If a masked loads is not added to the chain, it should not reset the chain's root. This fixes the remaining part of PR28515. llvm-svn: 275340
* Reverting r275284 due to platform-specific test failuresAndrew Kaylor2016-07-132-47/+0
| | | | llvm-svn: 275304
* Fix for Bug 26903, adds support to inline __builtin_mempcpyAndrew Kaylor2016-07-132-0/+47
| | | | | | | | Patch by Sunita Marathe Differential Revision: http://reviews.llvm.org/D21920 llvm-svn: 275284
* fix documentation comments; NFCSanjay Patel2016-07-111-42/+7
| | | | llvm-svn: 275101
* [DAG] make isConstantSplatVector() available to the rest of loweringSanjay Patel2016-07-102-32/+25
| | | | llvm-svn: 275025
* fix documentation comments; NFCSanjay Patel2016-07-101-11/+3
| | | | llvm-svn: 275021
* reformat, fix comments/names; NFCISanjay Patel2016-07-101-27/+22
| | | | llvm-svn: 275015
* Give helper classes/functions internal linkage. NFC.Benjamin Kramer2016-07-101-1/+1
| | | | llvm-svn: 275014
* fix documentation comments; NFCSanjay Patel2016-07-093-159/+143
| | | | llvm-svn: 274981
* Reapply r274829 with fix for FP vectorsMatt Arsenault2016-07-081-2/+4
| | | | llvm-svn: 274937
* Revert r274829, it caused PR28472.Nico Weber2016-07-081-1/+1
| | | | llvm-svn: 274916
* SelectionDAG: Avoid implicit iterator conversions in SelectionDAGBuilder, NFCDuncan P. N. Exon Smith2016-07-081-1/+2
| | | | llvm-svn: 274907
* SelectionDAG: Avoid implicit iterator conversions in SelectionDAGISel, NFCDuncan P. N. Exon Smith2016-07-081-8/+8
| | | | llvm-svn: 274904
* SelectionDAG: Avoid implicit iterator conversions in ScheduleDAGSDNodes, NFCDuncan P. N. Exon Smith2016-07-081-1/+1
| | | | llvm-svn: 274903
* SelectionDAG: Avoid implicit iterator conversions in FastISel, NFCDuncan P. N. Exon Smith2016-07-081-3/+4
| | | | llvm-svn: 274899
* Do not expand SDIV when compiling for minimum code sizeSjoerd Meijer2016-07-081-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D22139 llvm-svn: 274855
* Addressing post-commit comments regarding not expanding UDIV;Sjoerd Meijer2016-07-081-2/+2
| | | | | | we don't expand only when compiling for minimum code size. llvm-svn: 274847
* Code size optimisation: don't expand a div to a mul and and a shift sequence.Sjoerd Meijer2016-07-081-0/+5
| | | | | | | | | As a result, the urem instruction will not be expanded to a sequence of umull, lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod. Differential Revision: http://reviews.llvm.org/D22131 llvm-svn: 274843
* Bug 28444: Fix assertion when extract_vector_elt has mismatched typeMatt Arsenault2016-07-081-1/+1
| | | | | | | For some reason extract_vector_elt is sometimes allowed to have a different result type than the vector element type. llvm-svn: 274829
* Include SelectionDAGISel in the opt-bisect processAndrew Kaylor2016-07-071-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D21143 llvm-svn: 274786
* [DAGCombiner] Fix visitSTORE to continue processing current SDNode, if ↵Tim Shen2016-07-061-6/+12
| | | | | | | | | | | | | | | | | findBetterNeighborChains doesn't actually CombineTo it. Summary: findBetterNeighborChains may or may not find a better chain for each node it finds, which include the node ("St") that visitSTORE is currently processing. If no better chain is found for St, visitSTORE should continue instead of return SDValue(St, 0), as if it's CombinedTo'ed. This fixes bug 28130. There might be other ways to make the test pass (see D21409). I think both of the patches are fixing actual bugs revealed by the same testcase. Reviewers: echristo, wschmidt, hfinkel, kbarton, amehsan, arsenm, nemanjai, bogner Subscribers: mehdi_amini, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D21692 llvm-svn: 274644
* Revert r259387: "AArch64: Implement missed conditional compare sequences."Balaram Makam2016-07-051-2/+2
| | | | | | | This reverts commit r259387 because it inserts illegal code after legalization in some backends where i64 OR type is illegal for example. llvm-svn: 274573
* DAGCombiner: Fold away vector extract of insert with the same indexMatt Arsenault2016-07-051-0/+8
| | | | | | | This only really matters when the index is non-constant since the constant case already gets taken care of by other combines. llvm-svn: 274569
* [CodeGen] Make the code that detects a if a shuffle is really a ↵Craig Topper2016-07-041-33/+41
| | | | | | | | | | concatenation of the inputs more general purpose. We can now handle concatenation of each source multiple times. The previous code just checked for each source to appear once in either order. This also now handles an entire source vector sized piece having undef indices correctly. We now concat with UNDEF instead of using one of the sources. This is responsible for the test case change. llvm-svn: 274483
* [CodeGen] Teach OR combine of shuffles involving zero vectors to better ↵Craig Topper2016-07-031-5/+10
| | | | | | | | handle undef indices. Undef indices can now be treated as zeros. Or if its undef ORed with zero, we will keep the undef. llvm-svn: 274472
* [CodeGen] Cleanup getVectorShuffle a bit to take advantage of its new ↵Craig Topper2016-07-011-16/+16
| | | | | | ArrayRef argument and its begin/end iterators. Also use 'int' type for number of elements and loop iterators to remove several typecasts. No functional change intended. llvm-svn: 274338
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a ↵Craig Topper2016-07-016-30/+27
| | | | | | | | pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array. llvm-svn: 274337
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