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* A dbg.declare may not be in entry block, even if it is referring to an ↵Devang Patel2011-04-251-4/+0
| | | | | | incoming argument. However, It is appropriate to emit DBG_VALUE referring to this incoming argument in entry block in MachineFunction. llvm-svn: 130129
* Remove unused STL header includes.Jay Foad2011-04-231-1/+0
| | | | llvm-svn: 130068
* Teach FastISel to deal with instructions that have two immediate operands.Owen Anderson2011-04-221-10/+27
| | | | llvm-svn: 130033
* Recommit the fix for rdar://9289512 with a couple tweaks toChris Lattner2011-04-221-17/+54
| | | | | | | | | | | fix bugs exposed by the gcc dejagnu testsuite: 1. The load may actually be used by a dead instruction, which would cause an assert. 2. The load may not be used by the current chain of instructions, and we could move it past a side-effecting instruction. Change how we process uses to define the problem away. llvm-svn: 130018
* DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.Benjamin Kramer2011-04-221-0/+36
| | | | | | | | | | | | On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) llvm-svn: 130005
* Revert r1296656, "Fix rdar://9289512 - not folding load into compare at -O0...",Daniel Dunbar2011-04-211-41/+15
| | | | | | which broke a couple GCC test suite tests at -O0. llvm-svn: 129914
* Rewrite the expander for umulo/smulo to remember to sign extend the inputEric Christopher2011-04-201-10/+58
| | | | | | | | | manually and pass all (now) 4 arguments to the mul libcall. Add a new ExpandLibCall for just this (copied gratuitously from type legalization). Fixes rdar://9292577 llvm-svn: 129842
* Delete unnecessary variable. <rdar://problem/7662569>Stuart Hastings2011-04-191-11/+4
| | | | llvm-svn: 129796
* SelectBasicBlock is rather slow even when it doesn't do anything; skip theEli Friedman2011-04-191-5/+7
| | | | | | unnecessary work where possible. llvm-svn: 129763
* Support nested CALLSEQ_BEGIN/END; necessary for ARM byval support. ↵Stuart Hastings2011-04-191-42/+56
| | | | | | <rdar://problem/7662569> llvm-svn: 129761
* Implement support for x86 fastisel of small fixed-sized memcpys, which are ↵Chris Lattner2011-04-191-52/+44
| | | | | | | | | generated en-mass for C++ PODs. On my c++ test file, this cuts the fast isel rejects by 10x and shrinks the generated .s file by 5% llvm-svn: 129755
* while we're at it, handle 'sdiv exact' of a power of 2 also,Chris Lattner2011-04-181-0/+8
| | | | | | this fixes a few rejects on c++ iterator loops. llvm-svn: 129694
* fix rdar://9297011 - udiv by power of two causing fast-isel rejectsChris Lattner2011-04-181-0/+4
| | | | llvm-svn: 129693
* 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner2011-04-171-18/+30
| | | | | | | | | | 2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. llvm-svn: 129666
* fix an oversight which caused us to compile the testcase (and otherChris Lattner2011-04-171-5/+3
| | | | | | | | | | | | | | | | | | | less trivial things) into a dummy lea. Before we generated: _test: ## @test movq _G@GOTPCREL(%rip), %rax leaq (%rax), %rax ret now we produce: _test: ## @test movq _G@GOTPCREL(%rip), %rax ret This is part of rdar://9289558 llvm-svn: 129662
* Fix rdar://9289512 - not folding load into compare at -O0Chris Lattner2011-04-171-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | The basic issue here is that bottom-up isel is matching the branch and compare, and was failing to fold the load into the branch/compare combo. Fixing this (by allowing folding into any instruction of a sequence that is selected) allows us to produce things like: cmpb $0, 52(%rax) je LBB4_2 instead of: movb 52(%rax), %cl cmpb $0, %cl je LBB4_2 This makes the generated -O0 code run a bit faster, but also speeds up compile time by putting less pressure on the register allocator and generating less code. This was one of the biggest classes of missing load folding. Implementing this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm) line count. llvm-svn: 129656
* split a complex predicate out to a helper function. Simplify two for loops,Chris Lattner2011-04-171-10/+16
| | | | | | | which don't need to check for falling off the end of a block *and* end of phi nodes, since terminators are never phis. llvm-svn: 129655
* fix rdar://9289583 - fast isel should handle non-canonical commutative binopsChris Lattner2011-04-171-4/+23
| | | | | | | | | | allowing us to fold the immediate into the 'and' in this case: int test1(int i) { return 8&i; } llvm-svn: 129653
* PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.Eli Friedman2011-04-161-2/+2
| | | | | | | Returning a new node makes the code try to replace the old node, which in the included testcase is killed by CSE. llvm-svn: 129650
* Fix divmod libcall lowering. Convert to {S|U}DIVREM first and then expand ↵Evan Cheng2011-04-161-71/+65
| | | | | | the node to a libcall. rdar://9280991 llvm-svn: 129633
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-155-10/+9
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Fix another instance of the DAG combiner not using the correct type for the ↵Owen Anderson2011-04-141-3/+5
| | | | | | RHS of a shift. llvm-svn: 129522
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-142-13/+61
| | | | | | | | | | | | | | | | | | | | | | | | This is done by pushing physical register definitions close to their use, which happens to handle flag definitions if they're not glued to the branch. This seems to be generally a good thing though, so I didn't need to add a target hook yet. The primary motivation is to generate code closer to what people expect and rule out missed opportunity from enabling macro-op fusion. As a side benefit, we get several 2-5% gains on x86 benchmarks. There is one regression: SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is an independent scheduler bug that will be tracked separately. See rdar://problem/9283108. Incidentally, pre-RA scheduling is only half the solution. Fixing the later passes is tracked by: <rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump Fixes: <rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion llvm-svn: 129508
* sink a call into its only use.Chris Lattner2011-04-141-2/+1
| | | | llvm-svn: 129503
* During post-legalization DAG combining, be careful to only create shifts ↵Owen Anderson2011-04-131-1/+8
| | | | | | where the RHS is of the legal type for the new operation. llvm-svn: 129484
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-132-156/+190
| | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
* Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick2011-04-122-184/+157
| | | | llvm-svn: 129385
* PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick2011-04-122-157/+184
| | | | | | | | | | | | UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make these heuristic adjustments to node latency work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129383
* Don't include Operator.h from InstrTypes.h.Jay Foad2011-04-111-0/+1
| | | | llvm-svn: 129271
* Avoid excess precision issues that lead to generating host-compiler-specific ↵Chris Lattner2011-04-091-2/+6
| | | | | | | | code. Switch lowering probably shouldn't be using FP for this. This resolves PR9581. llvm-svn: 129199
* have dag combine zap "store undef", which can be formed during call loweringChris Lattner2011-04-091-2/+8
| | | | | | with undef arguments. llvm-svn: 129185
* Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng2011-04-081-2/+15
| | | | | | is lowered into a call to the specified trap function at sdisel time. llvm-svn: 129152
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-073-4/+107
| | | | | | | | | induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing llvm-svn: 129100
* Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling2011-04-051-1/+1
| | | | | | | | | | | | It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> llvm-svn: 128873
* Revert 123704; it broke threaded LLVM.Stuart Hastings2011-04-051-9/+15
| | | | llvm-svn: 128868
* Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich2011-04-021-0/+4
| | | | | | | | transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. llvm-svn: 128758
* Add comments.Evan Cheng2011-04-011-2/+4
| | | | llvm-svn: 128730
* Assign node order numbers to results of call instruction lowering. This ↵Evan Cheng2011-04-011-4/+8
| | | | | | should improve src line debug info when sdisel is used. rdar://9199118 llvm-svn: 128728
* Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng2011-04-012-19/+154
| | | | | | rdar://8911343 llvm-svn: 128696
* Turn SelectionDAGBuilder::GetRegistersForValue into a local function.Benjamin Kramer2011-03-262-19/+16
| | | | | | | | It couldn't be used outside of the file because SDISelAsmOperandInfo is local to SelectionDAGBuilder.cpp. Making it a static function avoids a weird linkage dance. llvm-svn: 128342
* Fix for -pre-RA-sched=source.Andrew Trick2011-03-251-0/+2
| | | | | | | Yet another case of unchecked NULL node (for physreg copy). May fix PR9509. llvm-svn: 128266
* PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND.Eli Friedman2011-03-232-60/+30
| | | | | | Also cleaning up some duplicated code while I'm here. llvm-svn: 128176
* Ensure that def-side physreg copies are scheduled above any other usesAndrew Trick2011-03-231-0/+9
| | | | | | | | | so the scheduler can't create new interferences on the copies themselves. Prior to this fix the scheduler could get stuck in a loop creating copies. Fixes PR9509. llvm-svn: 128164
* whitespaceAndrew Trick2011-03-231-2/+2
| | | | llvm-svn: 128163
* Added block number and name to isel debug output.Andrew Trick2011-03-231-12/+25
| | | | | | | | I'm tired of doing this manually for each checkout. If anyone knows a better way debug isel for non-trivial tests feel free to revert and let me know how to do it. llvm-svn: 128132
* Grammar-o.Eric Christopher2011-03-211-1/+1
| | | | llvm-svn: 128004
* Add support for legalizing UINT_TO_FP of vectors on platforms which doNadav Rotem2011-03-191-1/+48
| | | | | | | | not have native support for this operation (such as X86). The legalized code uses two vector INT_TO_FP operations and is faster than scalarizing. llvm-svn: 127951
* BuildUDIV: If the divisor is even we can simplify the fixup of the ↵Benjamin Kramer2011-03-171-9/+22
| | | | | | | | | | | | | | | | | | | | | | | multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
* Move more logic into getTypeForExtArgOrReturn.Cameron Zwarich2011-03-171-6/+2
| | | | llvm-svn: 127809
* Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().Cameron Zwarich2011-03-171-1/+1
| | | | llvm-svn: 127807
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