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* Tabs, formatting and long lines oh my!Eric Christopher2012-02-241-4/+6
| | | | llvm-svn: 151334
* Allow an integer to be converted into an MMX type when it's used in an inlineBill Wendling2012-02-231-2/+8
| | | | | | | asm. <rdar://problem/10106006> llvm-svn: 151303
* More newline cleanups.Eric Christopher2012-02-232-4/+4
| | | | llvm-svn: 151235
* Add some handy-dandy newlines.Eric Christopher2012-02-231-2/+2
| | | | llvm-svn: 151234
* Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer2012-02-223-16/+29
| | | | | | Patch by Joe Groff! llvm-svn: 151183
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-2/+2
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Teach the DAGCombiner that certain loadext nodes followed by ANDs can be ↵James Molloy2012-02-201-0/+82
| | | | | | converted to zeroexts. llvm-svn: 150957
* Ignore the lifetime intrinsics in fast-isel.Eric Christopher2012-02-171-0/+4
| | | | llvm-svn: 150848
* Remove extraneous #include and spelling mistake introduced in r150669.James Molloy2012-02-161-2/+1
| | | | llvm-svn: 150670
* Modify the algorithm when traversing the DAGCombiner's worklist to be O(log ↵James Molloy2012-02-161-13/+36
| | | | | | N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove. llvm-svn: 150669
* Added hook to let targets custom lower splitting of illegal vectorsPete Cooper2012-02-151-0/+4
| | | | llvm-svn: 150550
* Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem2012-02-141-1/+5
| | | | | | | | that are greater than the vector element type. For example BUILD_VECTOR of type <1 x i1> with a constant i8 operand. This patch fixes the assertion. llvm-svn: 150477
* Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames2012-02-143-3/+3
| | | | | | consistency with setExceptionPointerRegister(...). llvm-svn: 150460
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-0/+6
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49
| | | | | | | | | The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. llvm-svn: 150428
* Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem2012-02-131-2/+6
| | | | | | generate a shuffle node from two vectors of different types. llvm-svn: 150383
* This patch addresses the problem of poor code generation for the zextNadav Rotem2012-02-121-14/+29
| | | | | | | | | | | | | | | | | | | v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. llvm-svn: 150340
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-101-1/+1
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. llvm-svn: 150245
* [unwind removal] Remove all of the code for the dead 'unwind' instruction. ThereBill Wendling2012-02-063-7/+0
| | | | | | | were no 'unwind' instructions being generated before this, so this is in effect a no-op. llvm-svn: 149906
* Add additional documentation to the extract-and-trunc dagcombine optimization.Nadav Rotem2012-02-051-3/+8
| | | | llvm-svn: 149823
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-055-22/+20
| | | | llvm-svn: 149816
* reapply the patches reverted in r149470 that reenable ConstantDataArray,Chris Lattner2012-02-051-17/+15
| | | | | | | | | but with a critical fix to the SelectionDAG code that optimizes copies from strings into immediate stores: the previous code was stopping reading string data at the first nul. Address this by adding a new argument to llvm::getConstantStringInfo, preserving the behavior before the patch. llvm-svn: 149800
* [fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier2012-02-041-2/+2
| | | | llvm-svn: 149730
* Handle all live physreg defs in the same place.Jakob Stoklund Olesen2012-02-031-43/+46
| | | | | | | | | | | SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. llvm-svn: 149708
* The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem2012-02-031-0/+34
| | | | | | | | | extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. llvm-svn: 149692
* fix cmakeAndrew Trick2012-02-011-1/+1
| | | | llvm-svn: 149553
* VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick2012-02-014-1/+938
| | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
* SwitchInst refactoring.Stepan Dyatkovskiy2012-02-012-9/+9
| | | | | | | | | | | | | | | | | The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. llvm-svn: 149481
* Revert Chris' commits up to r149348 that started causing VMCoreTests unit ↵Argyrios Kyrtzidis2012-02-011-10/+7
| | | | | | | | | | | | | | | | | | | test to fail. These are: r149348 r149351 r149352 r149354 r149356 r149357 r149361 r149362 r149364 r149365 llvm-svn: 149470
* remove the last vestiges of llvm::GetConstantStringInfo, in CodeGen.Chris Lattner2012-01-311-7/+4
| | | | llvm-svn: 149356
* rework this logic to not depend on the last argument to GetConstantStringInfo,Chris Lattner2012-01-311-4/+10
| | | | | | which is going away. llvm-svn: 149348
* Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.Bill Wendling2012-01-312-91/+0
| | | | llvm-svn: 149331
* Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copyBill Wendling2012-01-312-53/+0
| | | | | | | over the catch information. The catch information is now tacked to the invoke instruction. llvm-svn: 149326
* Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. ↵Eli Friedman2012-01-311-7/+9
| | | | | | Not committing a testcase because I think it will be too fragile. llvm-svn: 149315
* continue making the world safe for ConstantDataVector. At this point,Chris Lattner2012-01-271-1/+1
| | | | | | | we should (theoretically optimize and codegen ConstantDataVector as well as ConstantVector. llvm-svn: 149116
* eliminate the Constant::getVectorElements method. There are better (andChris Lattner2012-01-261-13/+4
| | | | | | | more robust) ways to do what it was doing now. Also, add static methods for decoding a ShuffleVector mask. llvm-svn: 149028
* use ConstantVector::getSplat in a few places.Chris Lattner2012-01-251-1/+1
| | | | llvm-svn: 148929
* Use the right method to get the # elements in a CDS.Chris Lattner2012-01-251-1/+1
| | | | llvm-svn: 148897
* add more support for ConstantDataSequentialChris Lattner2012-01-241-2/+19
| | | | llvm-svn: 148802
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-206-21/+5
| | | | llvm-svn: 148578
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-184-2/+22
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
* Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem2012-01-181-2/+4
| | | | | | vector type to another, we must not bitcast the result if one type is widened while the other is promoted. llvm-svn: 148383
* Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper2012-01-181-7/+12
| | | | | | TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE llvm-svn: 148377
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-171-4/+35
| | | | llvm-svn: 148337
* Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper2012-01-171-4/+8
| | | | | | type. llvm-svn: 148297
* Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper2012-01-171-2/+3
| | | | | | checked for legalisation llvm-svn: 148275
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-161-2/+0
| | | | | | unused variables). llvm-svn: 148230
* Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper2012-01-161-1/+1
| | | | | | arithmetic so should not be checked in legalisation llvm-svn: 148228
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-5/+22
| | | | | | | | | | | We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-151-7/+5
| | | | | | CodeGen. llvm-svn: 148218
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