| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
|
|
|
|
| |
LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.
llvm-svn: 40807
|
| |
|
|
| |
llvm-svn: 40748
|
| |
|
|
| |
llvm-svn: 40722
|
| |
|
|
| |
llvm-svn: 40712
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)
Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)
And let scheduledag emit the move from X86::EAX to a virtual register.
llvm-svn: 40710
|
| |
|
|
| |
llvm-svn: 40682
|
| |
|
|
|
|
| |
- Fixed an existing unexpanded tab.
llvm-svn: 40605
|
| |
|
|
| |
llvm-svn: 40598
|
| |
|
|
|
|
| |
still under discussion.
llvm-svn: 40549
|
| |
|
|
|
|
|
| |
offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.
llvm-svn: 40534
|
| |
|
|
|
|
| |
instructions. PR1350
llvm-svn: 40520
|
| |
|
|
| |
llvm-svn: 40516
|
| |
|
|
|
|
| |
no public targets use this code-path, so no test.
llvm-svn: 40510
|
| |
|
|
| |
llvm-svn: 40480
|
| |
|
|
| |
llvm-svn: 40443
|
| |
|
|
|
|
| |
what it thought it was doing.
llvm-svn: 40044
|
| |
|
|
|
|
| |
alignment is equal to the stack alignment.
llvm-svn: 40004
|
| |
|
|
| |
llvm-svn: 39921
|
| |
|
|
| |
llvm-svn: 39856
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
|
| |
|
|
| |
llvm-svn: 39827
|
| |
|
|
|
|
| |
feedback. This theoretically makes the common (scalar) case more efficient.
llvm-svn: 39823
|
| |
|
|
|
|
|
| |
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
|
| |
|
|
|
|
|
| |
the new CONCAT_VECTORS node type instead, as that's what legalize
uses now. And add a peep for EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT.
llvm-svn: 38503
|
| |
|
|
| |
llvm-svn: 38496
|
| |
|
|
|
|
| |
Thanks to Lauro for spotting this!
llvm-svn: 38491
|
| |
|
|
|
|
| |
undef in either the left or right operand.
llvm-svn: 38489
|
| |
|
|
|
|
| |
should not be restricted to nodes that produce only a single value.
llvm-svn: 38485
|
| |
|
|
| |
llvm-svn: 38484
|
| |
|
|
|
|
| |
simplifying loads and stores.
llvm-svn: 38473
|
| |
|
|
|
|
|
|
| |
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
|
| |
|
|
|
|
|
|
|
|
|
| |
updating it with calls to setIndexedLoadAction/setIndexedStoreAction,
which only update a few bits at a time. This avoids ostensible
undefined behavior of operationg on values which may be
trap-representations, and as a practical matter fixes errors from
valgrind, which doesn't track uninitialized memory with bit
granularity.
llvm-svn: 38468
|
| |
|
|
|
|
|
|
|
| |
DAGCombiner.cpp: In member function 'llvm::SDOperand<unnamed>::DAGCombiner::visitOR(llvm::SDNode*)':
DAGCombiner.cpp:1608: warning: passing negative value '-0x00000000000000001' for argument 1 to 'llvm::SDOperand llvm::SelectionDAG::getConstant(uint64_t, llvm::MVT::ValueType, bool)'
oiy.
llvm-svn: 38458
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
so must be lowered to a value, not nothing at all.
Subtle point: I made eh_selector return 0 and
eh_typeid_for return 1. This means that only
cleanups (destructors) will be run as the exception
unwinds [if eh_typeid_for returned 0 then it would
be as if the first catch always matched, and the
corresponding handler would be run], which is
probably want you want in the CBE.
llvm-svn: 37947
|
| |
|
|
| |
llvm-svn: 37940
|
| |
|
|
|
|
| |
fix, that is adequate while PR1508 remains unresolved.
llvm-svn: 37938
|
| |
|
|
|
|
| |
instead.
llvm-svn: 37937
|
| |
|
|
| |
llvm-svn: 37935
|
| |
|
|
| |
llvm-svn: 37934
|
| |
|
|
| |
llvm-svn: 37922
|
| |
|
|
|
|
|
|
| |
endian swapping should be done, and update the code to use it. This fixes
some register ordering issues on big-endian systems, such as PowerPC,
introduced by the recent illegal by-val arguments changes.
llvm-svn: 37921
|
| |
|
|
|
|
| |
Drop the eh.filter intrinsic.
llvm-svn: 37875
|
| |
|
|
|
|
| |
follow the rules for undef used in instcombine.
llvm-svn: 37851
|
| |
|
|
|
|
|
| |
model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
|
| |
|
|
|
|
|
|
| |
refactored getCopyFromParts and getCopyToParts, which are more general.
This effectively adds support for lowering illegal by-val vector call
arguments.
llvm-svn: 37843
|
| |
|
|
|
|
|
|
|
|
| |
visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.
This fixes test/CodeGen/X86/negative-sin.ll.
llvm-svn: 37842
|
| |
|
|
| |
llvm-svn: 37818
|
| |
|
|
| |
llvm-svn: 37816
|
| |
|
|
| |
llvm-svn: 37814
|
| |
|
|
| |
llvm-svn: 37799
|