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* [DAG] Remove redundant FMUL in Newton-Raphson SQRT codeSanjay Patel2016-06-161-53/+86
| | | | | | | | | | | | | | | | | When calculating a square root using Newton-Raphson with two constants, a naive implementation is to use five multiplications (four muls to calculate reciprocal square root and another one to calculate the square root itself). However, after some reassociation and CSE the same result can be obtained with only four multiplications. Unfortunately, there's no reliable way to do such a reassociation in the back-end. So, the patch modifies NR code itself so that it directly builds optimal code for SQRT and doesn't rely on any further reassociation. Patch by Nikolai Bozhenov! Differential Revision: http://reviews.llvm.org/D21127 llvm-svn: 272920
* Revert "Preserve DebugInfo when replacing values in DAGCombiner"Nirav Dave2016-06-153-18/+7
| | | | | | | | | Reverting due to assertion failure in lib/CodeGen/SelectionDAG/InstrEmitter.cpp This reverts commit r272792. llvm-svn: 272799
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-153-7/+18
| | | | | | | | | | | | | | | | | | | [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 272792
* [X86] Reduce the width of multiplification when its operands are extended ↵Wei Mi2016-06-141-0/+2
| | | | | | | | | | | | | | | | from i8 or i16 For <N x i32> type mul, pmuludq will be used for targets without SSE41, which often introduces many extra pack and unpack instructions in vectorized loop body because pmuludq generates <N/2 x i64> type value. However when the operands of <N x i32> mul are extended from smaller size values like i8 and i16, the type of mul may be shrunk to use pmullw + pmulhw/pmulhuw instead of pmuludq, which generates better code. For targets with SSE41, pmulld is supported so no shrinking is needed. Differential Revision: http://reviews.llvm.org/D20931 llvm-svn: 272694
* [SelectionDAG] Remove exit-on-error flag from test (PR27765)Diana Picus2016-06-141-1/+3
| | | | | | | | | | | | | | | | The exit-on-error flag in the ARM test is necessary in order to avoid an unreachable in the DAGTypeLegalizer, when trying to expand a physical register. We can also avoid this situation by introducing a bitcast early on, where the invalid scalar-to-vector conversion is detected. We also add a test for PowerPC, which goes through a similar code path in the SelectionDAGBuilder. Fixes PR27765. Differential Revision: http://reviews.llvm.org/D21061 llvm-svn: 272644
* This patch fixes handling long double type when it isStrahinja Petrovic2016-06-131-3/+20
| | | | | | constant in soft float mode on PowerPC 32 architecture. llvm-svn: 272543
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-1213-413/+376
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* SelectionDAG: Implement expansion of {S,U}MIN/MAX in integer legalizationJan Vesely2016-06-092-0/+55
| | | | | | | | | Fixes {u,}long_{min,max,clamp} opencl piglit regressions on EG. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D17898 llvm-svn: 272272
* Avoid copies of std::strings and APInt/APFloats where we only read from itBenjamin Kramer2016-06-082-6/+6
| | | | | | | | As suggested by clang-tidy's performance-unnecessary-copy-initialization. This can easily hit lifetime issues, so I audited every change and ran the tests under asan, which came back clean. llvm-svn: 272126
* [stack-protection] Add support for MSVC buffer security checkEtienne Bergeron2016-06-073-14/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch is adding support for the MSVC buffer security check implementation The buffer security check is turned on with the '/GS' compiler switch. * https://msdn.microsoft.com/en-us/library/8dbf701c.aspx * To be added to clang here: http://reviews.llvm.org/D20347 Some overview of buffer security check feature and implementation: * https://msdn.microsoft.com/en-us/library/aa290051(VS.71).aspx * http://www.ksyash.com/2011/01/buffer-overflow-protection-3/ * http://blog.osom.info/2012/02/understanding-vs-c-compilers-buffer.html For the following example: ``` int example(int offset, int index) { char buffer[10]; memset(buffer, 0xCC, index); return buffer[index]; } ``` The MSVC compiler is adding these instructions to perform stack integrity check: ``` push ebp mov ebp,esp sub esp,50h [1] mov eax,dword ptr [__security_cookie (01068024h)] [2] xor eax,ebp [3] mov dword ptr [ebp-4],eax push ebx push esi push edi mov eax,dword ptr [index] push eax push 0CCh lea ecx,[buffer] push ecx call _memset (010610B9h) add esp,0Ch mov eax,dword ptr [index] movsx eax,byte ptr buffer[eax] pop edi pop esi pop ebx [4] mov ecx,dword ptr [ebp-4] [5] xor ecx,ebp [6] call @__security_check_cookie@4 (01061276h) mov esp,ebp pop ebp ret ``` The instrumentation above is: * [1] is loading the global security canary, * [3] is storing the local computed ([2]) canary to the guard slot, * [4] is loading the guard slot and ([5]) re-compute the global canary, * [6] is validating the resulting canary with the '__security_check_cookie' and performs error handling. Overview of the current stack-protection implementation: * lib/CodeGen/StackProtector.cpp * There is a default stack-protection implementation applied on intermediate representation. * The target can overload 'getIRStackGuard' method if it has a standard location for the stack protector cookie. * An intrinsic 'Intrinsic::stackprotector' is added to the prologue. It will be expanded by the instruction selection pass (DAG or Fast). * Basic Blocks are added to every instrumented function to receive the code for handling stack guard validation and errors handling. * Guard manipulation and comparison are added directly to the intermediate representation. * lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp * lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp * There is an implementation that adds instrumentation during instruction selection (for better handling of sibbling calls). * see long comment above 'class StackProtectorDescriptor' declaration. * The target needs to override 'getSDagStackGuard' to activate SDAG stack protection generation. (note: getIRStackGuard MUST be nullptr). * 'getSDagStackGuard' returns the appropriate stack guard (security cookie) * The code is generated by 'SelectionDAGBuilder.cpp' and 'SelectionDAGISel.cpp'. * include/llvm/Target/TargetLowering.h * Contains function to retrieve the default Guard 'Value'; should be overriden by each target to select which implementation is used and provide Guard 'Value'. * lib/Target/X86/X86ISelLowering.cpp * Contains the x86 specialisation; Guard 'Value' used by the SelectionDAG algorithm. Function-based Instrumentation: * The MSVC doesn't inline the stack guard comparison in every function. Instead, a call to '__security_check_cookie' is added to the epilogue before every return instructions. * To support function-based instrumentation, this patch is * adding a function to get the function-based check (llvm 'Value', see include/llvm/Target/TargetLowering.h), * If provided, the stack protection instrumentation won't be inlined and a call to that function will be added to the prologue. * modifying (SelectionDAGISel.cpp) do avoid producing basic blocks used for inline instrumentation, * generating the function-based instrumentation during the ISEL pass (SelectionDAGBuilder.cpp), * if FastISEL (not SelectionDAG), using the fallback which rely on the same function-based implemented over intermediate representation (StackProtector.cpp). Modifications * adding support for MSVC (lib/Target/X86/X86ISelLowering.cpp) * adding support function-based instrumentation (lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp, .h) Results * IR generated instrumentation: ``` clang-cl /GS test.cc /Od /c -mllvm -print-isel-input ``` ``` *** Final LLVM Code input to ISel *** ; Function Attrs: nounwind sspstrong define i32 @"\01?example@@YAHHH@Z"(i32 %offset, i32 %index) #0 { entry: %StackGuardSlot = alloca i8* <<<-- Allocated guard slot %0 = call i8* @llvm.stackguard() <<<-- Loading Stack Guard value call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot) <<<-- Prologue intrinsic call (store to Guard slot) %index.addr = alloca i32, align 4 %offset.addr = alloca i32, align 4 %buffer = alloca [10 x i8], align 1 store i32 %index, i32* %index.addr, align 4 store i32 %offset, i32* %offset.addr, align 4 %arraydecay = getelementptr inbounds [10 x i8], [10 x i8]* %buffer, i32 0, i32 0 %1 = load i32, i32* %index.addr, align 4 call void @llvm.memset.p0i8.i32(i8* %arraydecay, i8 -52, i32 %1, i32 1, i1 false) %2 = load i32, i32* %index.addr, align 4 %arrayidx = getelementptr inbounds [10 x i8], [10 x i8]* %buffer, i32 0, i32 %2 %3 = load i8, i8* %arrayidx, align 1 %conv = sext i8 %3 to i32 %4 = load volatile i8*, i8** %StackGuardSlot <<<-- Loading Guard slot call void @__security_check_cookie(i8* %4) <<<-- Epilogue function-based check ret i32 %conv } ``` * SelectionDAG generated instrumentation: ``` clang-cl /GS test.cc /O1 /c /FA ``` ``` "?example@@YAHHH@Z": # @"\01?example@@YAHHH@Z" # BB#0: # %entry pushl %esi subl $16, %esp movl ___security_cookie, %eax <<<-- Loading Stack Guard value movl 28(%esp), %esi movl %eax, 12(%esp) <<<-- Store to Guard slot leal 2(%esp), %eax pushl %esi pushl $204 pushl %eax calll _memset addl $12, %esp movsbl 2(%esp,%esi), %esi movl 12(%esp), %ecx <<<-- Loading Guard slot calll @__security_check_cookie@4 <<<-- Epilogue function-based check movl %esi, %eax addl $16, %esp popl %esi retl ``` Reviewers: kcc, pcc, eugenis, rnk Subscribers: majnemer, llvm-commits, hans, thakis, rnk Differential Revision: http://reviews.llvm.org/D20346 llvm-svn: 272053
* Re-apply "SDAG: Update ChainNodesMatched as nodes are deleted"Justin Bogner2016-06-031-4/+9
| | | | | | | | | | | | | | | My first attempt at this had an overly aggressive assert - chain nodes will only be removed, but we could hit the assert if a non-chain node was CSE'd (NodeToMatch, for instance). This reapplies r271706 by reverting r271713 and fixing an assert. Original message: Avoid relying on UB by looking into deleted nodes for a marker value. Instead, update the list of chain nodes as we go. llvm-svn: 271733
* Revert "SDAG: Update ChainNodesMatched as nodes are deleted"Justin Bogner2016-06-031-9/+4
| | | | | | | | | Seeing failures in CodeGen/Generic/icmp-illegal.ll on quite a few bots. This reverts r271706. llvm-svn: 271713
* SDAG: Update ChainNodesMatched as nodes are deletedJustin Bogner2016-06-031-4/+9
| | | | | | | Avoid relying on UB by looking into deleted nodes for a marker value. Instead, update the list of chain nodes as we go. llvm-svn: 271706
* SDAG: Replace some unreachable code with an assert. NFCJustin Bogner2016-06-031-6/+3
| | | | | | | The current node shouldn't be (and isn't) removed partway through selection. llvm-svn: 271699
* transform obscured FP sign bit ops into a fabs/fneg using TLI hookSanjay Patel2016-06-021-0/+46
| | | | | | | | | | | | | | | | | | | This is effectively a revert of: http://reviews.llvm.org/rL249702 - [InstCombine] transform masking off of an FP sign bit into a fabs() intrinsic call (PR24886) and: http://reviews.llvm.org/rL249701 - [ValueTracking] teach computeKnownBits that a fabs() clears sign bits and a reimplementation as a DAG combine for targets that have IEEE754-compliant fabs/fneg instructions. This is intended to resolve the objections raised on the dev list: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098154.html and: https://llvm.org/bugs/show_bug.cgi?id=24886#c4 In the interest of patch minimalism, I've only partly enabled AArch64. PowerPC, MIPS, x86 and others can enable later. Differential Revision: http://reviews.llvm.org/D19391 llvm-svn: 271573
* [DAG] use getBitcast() to reduce codeSanjay Patel2016-06-021-33/+25
| | | | | | | | | | Although this was intended to be NFC, the test case wiggle shows a change in code scheduling/RA caused by a difference in the SDLoc() generation. Depending on how you look at it, this is the (dis)advantage of exact checking in regression tests. llvm-svn: 271526
* SDAG: Drop a redundant replace and move the dead node removal closer. NFCJustin Bogner2016-06-011-6/+4
| | | | llvm-svn: 271429
* [DAG] Improve legalization of INSERT_SUBVECTORMichael Kuperstein2016-06-011-3/+22
| | | | | | | | | When the index is known to be constant 0, insert directly into the the low half, instead of spilling, performing the insert in-memory, and reloading. Differential Revision: http://reviews.llvm.org/D20763 llvm-svn: 271428
* DAGCombiner: Fix broken size check in isAliasMatt Arsenault2016-06-011-1/+1
| | | | | | | | | | | | | | | This should have been converting the size to bytes, but wasn't really. These should probably all be using getStoreSize instead. I haven't been able to come up with a meaningful testcase for this. I can trigger it using combinations of struct loads and stores, but can't observe a difference in non-broken testcases. isAlias is only really used during store merging, so I'm not sure how to get into the vector splitting situation the comment describes since store merging is only done before type legalization. llvm-svn: 271356
* [CodeGen] Promote FMINNAN/FMAXNAN like other binops.Ahmed Bougacha2016-05-311-0/+2
| | | | | | | | We think it's OK to generate half fminnan because it's legal for the transform-to type (f32; r245196). However, PromoteFloatRes was missing the case; simply promote like the other binops, including minnum. llvm-svn: 271317
* [X86] Detect SAD patterns and emit psadbw instructions.Michael Kuperstein2016-05-271-7/+11
| | | | | | | | This recommits r267649 with a fix for PR27539. Differential Revision: http://reviews.llvm.org/D20598 llvm-svn: 271033
* Apply clang-tidy's misc-move-constructor-init throughout LLVM.Benjamin Kramer2016-05-272-11/+17
| | | | | | No functionality change intended, maybe a tiny performance improvement. llvm-svn: 270997
* SDAG: Use an Optional<> instead of a sigil value. NFCJustin Bogner2016-05-261-6/+6
| | | | | | | This just makes it a bit more clear that we don't intend to use a deleted node for anything here. llvm-svn: 270931
* Simplify std::all_of predicate (to one line) by using llvm::all_of. NFCI.Simon Pilgrim2016-05-251-2/+1
| | | | llvm-svn: 270749
* Simplify std::all_of predicate (to one line) by using llvm::all_of. NFCI.Simon Pilgrim2016-05-251-3/+1
| | | | llvm-svn: 270747
* [SelectionDAG] Add smarts for BSWAP in computeKnownBits.Chad Rosier2016-05-251-0/+6
| | | | llvm-svn: 270738
* [SDAG] Add a fallback multiplication expansionHal Finkel2016-05-251-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | LegalizeIntegerTypes does not have a way to expand multiplications for large integer types (i.e. larger than twice the native bit width). There's no standard runtime call to use in that case, and so we'd just assert. Unfortunately, as it turns out, it is possible to hit this case from standard-ish C code in rare cases. A particular case a user ran into yesterday involved an __int128 induction variable and a loop with a quadratic (not linear) recurrence which triggered some backend logic using SCEVExpander. In this case, the BinomialCoefficient code in SCEV generates some i129 variables, which get widened to i256. At a high level, this is not actually good (i.e. the underlying optimization, PPCLoopPreIncPrep, should not be transforming the loop in question for performance reasons), but regardless, the backend shouldn't crash because of cost-modeling issues in the optimizer. This is a straightforward implementation of the multiplication expansion, based on the algorithm in Hacker's Delight. I validated it against the code for the mul256b function from http://locklessinc.com/articles/256bit_arithmetic/ using random inputs. There should be no functional change for previously-working code (the new expansion code only replaces an assert). Fixes PR19797. llvm-svn: 270720
* Fix some comment typos in SelectionDAGBuilder. NFCDiana Picus2016-05-201-3/+3
| | | | llvm-svn: 270190
* [SelectionDAG] rename/move isKnownToBeAPowerOfTwo() from TargetLowering (NFC)Sanjay Patel2016-05-192-32/+30
| | | | | | | | | There are at least 2 places (DAGCombiner, X86ISelLowering) where this could be used instead of ad-hoc and watered down code that is trying to match a power-of-2 pattern. Differential Revision: http://reviews.llvm.org/D20439 llvm-svn: 270073
* reduce indentation; NFCISanjay Patel2016-05-191-9/+7
| | | | llvm-svn: 270007
* Fix an assert in SelectionDAGBuilder when processing inline asmRenato Golin2016-05-172-25/+30
| | | | | | | | | | | | | | When processing inline asm that contains errors, make sure we can recover gracefully by creating an UNDEF SDValue for the inline asm statement before returning from SelectionDAGBuilder::visitInlineAsm. This is necessary for consumers that don't exit on the first error that is emitted (e.g. clang) and that would assert later on. Fixes PR24071. Patch by Diana Picus. llvm-svn: 269811
* SelectionDAG: Select min/max when both are usedMatt Arsenault2016-05-161-1/+9
| | | | | | | | | | | Allow two users of the condition if the other user is also a min/max select. i.e. %c = icmp slt i32 %x, %y %min = select i1 %c, i32 %x, i32 %y %max = select i1 %c, i32 %y, i32 %x llvm-svn: 269699
* Remove extra whitespace. NFC.Chad Rosier2016-05-161-1/+1
| | | | llvm-svn: 269685
* [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP ↵Simon Pilgrim2016-05-121-5/+32
| | | | | | | | | | | | | | and BITREVERSE stages For BITREVERSE, bit shifting/masking every bit in a vector element is a very lengthy procedure. If the input vector type is a whole multiple of bytes wide then we can split this into a BSWAP shuffle stage (to reverse at the byte level) and then a BITREVERSE stage applied to each byte. Most vector capable targets can efficiently BSWAP using shuffles resulting in a considerable reduction in instructions. With this patch targets would only need to implement a target specific vXi8 BITREVERSE implementation to efficiently reverse most legal vector types. Differential Revision: http://reviews.llvm.org/D19978 llvm-svn: 269290
* SDAG: Have SelectNodeTo replace uses if it CSE's instead of morphing a nodeJustin Bogner2016-05-112-9/+8
| | | | | | | | It's awkward to force callers of SelectNodeTo to figure out whether the node was morphed or CSE'd. Update uses here instead of requiring callers to (sometimes) do it. llvm-svn: 269235
* fix typos in comments; NFCSanjay Patel2016-05-111-41/+40
| | | | llvm-svn: 269206
* SDAG: Make SelectCodeCommon return voidJustin Bogner2016-05-101-25/+41
| | | | | | | | | | | This means SelectCode unconditionally returns nullptr now. I'll follow up with a change to make that return void as well, but it seems best to keep that one very mechanical. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269136
* [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.Marcin Koscielnicki2016-05-101-4/+17
| | | | | | | | | | | | Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign extended result, or a zero extended result. SystemZ takes a third option by returning junk in the high bits (rotated contents of the other bytes in the memory word). In that case, don't use Assert*ext, and zero-extend the result ourselves if a comparison is needed. Differential Revision: http://reviews.llvm.org/D19800 llvm-svn: 269075
* [TargetLowering] make helper function for SetCC + and optimizations (NFC)Sanjay Patel2016-05-091-52/+40
| | | | | | | | | | After looking at D19087 again, it occurred to me that we can do better. If we consolidate the valueHasExactlyOneBitSet() transforms, we won't incur extra overhead from calling it a 2nd time, and we can shrink SimplifySetCC() a bit. No functional change intended. Differential Revision: http://reviews.llvm.org/D20050 llvm-svn: 268932
* Fix unused variable warning.Simon Pilgrim2016-05-071-1/+0
| | | | llvm-svn: 268867
* [SelectionDAG] Added bitreverse(bitreverse(v)) --> vSimon Pilgrim2016-05-072-0/+18
| | | | | | Added bitreverse creation testing llvm-svn: 268865
* [x86, BMI] add TLI hook for 'andn' and use it to simplify comparisonsSanjay Patel2016-05-071-0/+49
| | | | | | | | | | | | | | | | | | | | | For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
* SDAG: Don't leave dangling dead nodes after SelectCodeCommonJustin Bogner2016-05-061-1/+3
| | | | | | | Relying on the caller to clean up after we've replaced all uses of a node won't work when we've migrated to the `void Select(...)` API. llvm-svn: 268774
* [CodeGen] Round [SU]INT_TO_FP result when promoting from f16.Ahmed Bougacha2016-05-061-1/+6
| | | | | | | | | | | | If we don't, values that aren't precisely representable in f16 could be used as-is in a promoted f32 operation, which would produce incorrect results. AArch64 had the correct behavior; add a focused test. Fixes http://llvm.org/PR26871 llvm-svn: 268700
* SDAG: Rename Select->SelectImpl and repurpose Select as returning voidJustin Bogner2016-05-051-17/+1
| | | | | | | | | | | | | | This is a step towards removing the rampant undefined behaviour in SelectionDAG, which is a part of llvm.org/PR26808. We rename SelectionDAGISel::Select to SelectImpl and update targets to match, and then change Select to return void and consolidate the sketchy behaviour we're trying to get away from there. Next, we'll update backends to implement `void Select(...)` instead of SelectImpl and eventually drop the base Select implementation. llvm-svn: 268693
* SDAG: Remove OPC_MarkGlueResults and associated logic. NFCJustin Bogner2016-05-051-60/+19
| | | | | | | | | This opcode never happens in practice, and yet the logic we have in place to handle it would be undefined behaviour if we ever executed it. Remove it rather than trying to refactor code that's never reached. llvm-svn: 268692
* clean up; NFCISanjay Patel2016-05-041-15/+15
| | | | llvm-svn: 268564
* [SelectionDAG] BITREVERSE vector legalization of bit operations (REAPPLIED)Simon Pilgrim2016-05-041-2/+2
| | | | | | | | Some vector bit operations are promoted instead of having custom lowering. This patch changes the isOperationLegalOrCustom tests for vector AND/OR operations to use a new TLI helper isOperationLegalOrCustomOrPromote instead, allowing the SSE implementations to stay on the simd unit. Differential Revision: http://reviews.llvm.org/D19805 llvm-svn: 268561
* Revert r268504Simon Pilgrim2016-05-041-2/+2
| | | | llvm-svn: 268526
* [SelectionDAG] BITREVERSE vector legalization of bit operationsSimon Pilgrim2016-05-041-2/+2
| | | | | | | | Vector bit operations are typically promoted instead of having custom lowering. This patch changes the isOperationLegalOrCustom tests for vector AND/OR operations to use isOperationLegalOrPromote instead, allowing the SSE implementations to stay on the simd unit. Differential Revision: http://reviews.llvm.org/D19805 llvm-svn: 268504
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