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* [DAG] Defer merge store cycle checking to just before merge. NFCI.Nirav Dave2018-05-161-8/+20
| | | | llvm-svn: 332489
* [AArch64] Gangup loads and stores for pairing.Sirish Pande2018-05-161-4/+85
| | | | | | | | | | Keep loads and stores together (target defines how many loads and stores to gang up), such that it will help in pairing and vectorization. Differential Revision https://reviews.llvm.org/D46477 llvm-svn: 332482
* Emit a left-shift instead of a power-of-two multiply for jump-tablesAlexander Richardson2018-05-161-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SelectionDAGLegalize::ExpandNode() inserts an ISD::MUL when lowering a BR_JT opcode. While many backends optimize this multiply into a shift, e.g. the MIPS backend currently always lowers this into a sequence of load-immediate+multiply+mflo in MipsSETargetLowering::lowerMulDiv(). I initially changed the multiply to a shift in the MIPS backend but it turns out that would not have handled the MIPSR6 case and was a lot more code than doing it in LegalizeDAG. I believe performing this simple optimization in LegalizeDAG instead of each individual backend is the better solution since this also fixes other backeds such as MSP430 which calls the multiply runtime function __mspabi_mpyi without this patch. Reviewers: sdardis, atanasyan, pftbest, asl Reviewed By: sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45760 llvm-svn: 332439
* [DAGCombine] Move load checks on store of loads into candidateNirav Dave2018-05-151-15/+13
| | | | | | | | | | search. NFCI. Migrate single-use and non-volatility, non-indexed requirements on stores of immediate store values to candidate collection pass from later stage. llvm-svn: 332392
* [DAG] propagate FMF for all FPMathOperatorsSanjay Patel2018-05-152-12/+29
| | | | | | | | | | | | | | | | | This is a simple hack based on what's proposed in D37686, but we can extend it if needed in follow-ups. It gets us most of the FMF functionality that we want without adding any state bits to the flags. It also intentionally leaves out non-FMF flags (nsw, etc) to minimize the patch. It should provide a superset of the functionality from D46563 - the extra tests show propagation and codegen diffs for fcmp, vecreduce, and FP libcalls. The PPC log2() test shows the limits of this most basic approach - we only applied 'afn' to the last node created for the call. AFAIK, there aren't any libcall optimizations based on the flags currently, so that shouldn't make any difference. Differential Revision: https://reviews.llvm.org/D46854 llvm-svn: 332358
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-1416-379/+362
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [DAG] add convenience function to propagate FMF; NFCSanjay Patel2018-05-111-7/+1
| | | | | | | | | There's only one use of this currently, but that could change with D46563. Either way, we shouldn't have to update code outside of the flags struct when those flag definitions change. llvm-svn: 332155
* [DAG] clean up flag propagation for binops; NFCISanjay Patel2018-05-112-36/+22
| | | | llvm-svn: 332150
* [DAG] reduce code duplication; NFCISanjay Patel2018-05-111-8/+7
| | | | llvm-svn: 332133
* [DAGCombiner] Set the right SDLoc on extended SETCC uses (7/N)Vedant Kumar2018-05-111-19/+13
| | | | | | | | | | | | | | | | | | | | ExtendSetCCUses updates SETCC nodes which use a load (OriginalLoad) to reflect a simplification to the load (ExtLoad). Based on my reading, ExtendSetCCUses may create new nodes to extend a constant attached to a SETCC. It also creates fresh SETCC nodes which refer to any updated operands. ISTM that the location applied to the new constant and SETCC nodes should be the same as the location of the ExtLoad. This was suggested by Adrian in https://reviews.llvm.org/D45995. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46216 llvm-svn: 332119
* [DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N)Vedant Kumar2018-05-111-38/+8
| | | | | | | | | | | | | | | | This teaches tryToFoldExtOfLoad to set the right location on a newly-created extload. With that in place, the logic for performing a certain ([s|z]ext (load ...)) combine becomes identical for sexts and zexts, and we can get rid of one copy of the logic. The test case churn is due to dependencies on IROrders inherited from the wrong SDLoc. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46158 llvm-svn: 332118
* [DAGCombiner] Factor out duplicated logic for an extload combine, NFC (5/N)Vedant Kumar2018-05-111-38/+52
| | | | | | | | | | | | | | | | Part of the logic for combining (zext (load ...)) and (sext (load ...)) is duplicated. This creates problems because bugs in one version have to be fixed again in the other version. To address this, as a first step, I've extracted the duplicate logic into a helper. I'll fix the debug location bug in the helper and eliminate the copy of its logic in a followup. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46157 llvm-svn: 332117
* [STLExtras] Add distance() for ranges, pred_size(), and succ_size()Vedant Kumar2018-05-101-2/+1
| | | | | | | | | | | This commit adds a wrapper for std::distance() which works with ranges. As it would be a common case to write `distance(predecessors(BB))`, this also introduces `pred_size()` and `succ_size()` helpers to make that easier to write. Differential Revision: https://reviews.llvm.org/D46668 llvm-svn: 332057
* [DAG] Avoid using deleted node in rebuildSetCCNirav Dave2018-05-101-8/+21
| | | | | | | | | | | | | | | | | Summary: The combine in rebuildSetCC may be combined to another node leaving our references stale. Keep a handle on it to avoid stale references. Fixes PR36602. Reviewers: dbabokin, RKSimon, eli.friedman, davide Subscribers: hiraditya, uabelho, JesperAntonsson, qcolombet, llvm-commits Differential Revision: https://reviews.llvm.org/D46404 llvm-svn: 331985
* [DAGCombiner] In visitBITCAST when trying to constant fold the bitcast, only ↵Craig Topper2018-05-091-11/+11
| | | | | | | | | | call getBitcast if its an fp->int or int->fp conversion even when before legalize ops. Previously if !LegalOperations we would blindly call getBitcast and hope that getNode would constant fold it. But if the conversion is between a vector and a scalar, getNode has no simplification. This means we would just get back the original N. We would then return that N which would make the caller of visitBITCAST think that we used CombineTo and did our own worklist management. This prevents target specific optimizations from being called for vector/scalar bitcasts until after legal operations. llvm-svn: 331896
* [DAGCombine] Change store merge candidates check cut off to 1024.Amara Emerson2018-05-091-1/+1
| | | | | | | | | | | The previous value of 8192 resulted in severe compile time hits in some pathological cases. rdar://39781410 Differential Revision: https://reviews.llvm.org/D46581 llvm-svn: 331888
* [DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr.Shiva Chen2018-05-096-0/+94
| | | | | | | | | | | | | | | | | | | | | In order to convert LLVM IR to MachineInstr, we need a new TargetOpcode, DBG_LABEL, to ‘lower’ intrinsic llvm.dbg.label. The patch creates this new TargetOpcode and convert intrinsic llvm.dbg.label to MachineInstr through SelectionDAG. In SelectionDAG, debug information is stored in SDDbgInfo. We create a new data member of SDDbgInfo for labels and use the new data member, SDDbgLabel, to create DBG_LABEL MachineInstr. The new DBG_LABEL MachineInstr uses label metadata from LLVM IR as its parameter. So, the backend could get metadata information of labels from DBG_LABEL MachineInstr. Differential Revision: https://reviews.llvm.org/D45341 Patch by Hsiangkai Wang. llvm-svn: 331842
* DAG: Use correct shift width typeMatt Arsenault2018-05-081-1/+1
| | | | llvm-svn: 331792
* [DAGCombiner] Masked merge: enhance handling of 'andn' with immediatesRoman Lebedev2018-05-071-4/+14
| | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. The previous patch, D46493, completely disabled unfolding in case of immediates. But we can do better: {F6120274} {F6120277} https://rise4fun.com/Alive/xJS Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D46494 llvm-svn: 331685
* [DagCombiner] Not all 'andn''s work with immediates.Roman Lebedev2018-05-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. In masked merge case, this degrades IPC by decreasing instruction count. {F6108777} The next patch should be able to recover and improve this. This also affects the transform @spatel have added in D27489 / rL289738, and the test coverage for X86 was missing. But after i have added it, and looked at the changes in MCA, i'm somewhat confused. {F6093591} {F6093592} {F6093593} I'd say this regression is an improvement, since `IPC` increased in that case? Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D46493 llvm-svn: 331684
* [SelectionDAG] Transfer DbgValues when casts are optimized in ↵Aaron Smith2018-05-071-2/+4
| | | | | | | | | | | | | | | | | | | | | SelectionDAG::getNode Summary: getNode optimizes (ext (trunc x)) to x and the dbgvalue node on trunc is lost. The fix calls transferDbgValues to add the dbgvalue to x. Add DebugInfo/AArch64/dbg-value-i16.ll Patch by Sejong Oh! Reviewers: aprantl, javed.absar, llvm-commits, vsk Reviewed By: aprantl, vsk Subscribers: kristof.beyls, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46348 llvm-svn: 331665
* [NFC][DAGCombine] unfoldMaskedMerge(): rename two variablesRoman Lebedev2018-05-061-4/+4
| | | | | | | The current names can be confused with the A and B sides of the canonical masked merge pattern. llvm-svn: 331609
* [DAGCombiner] Masked merge: don't touch "not" xor's.Roman Lebedev2018-05-051-0/+10
| | | | | | | | | | | | | | | | | | | | Summary: Split off form D46031. It seems we don't want to transform the pattern if the `xor`'s are actually `not`'s. In vector case, this breaks `andnpd` / `vandnps` patterns. That being said, we may want to re-visit this `not` handling, maybe in D46073. Reviewers: spatel, craig.topper, javed.absar Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46492 llvm-svn: 331595
* [NFC][DagCombiner] unfoldMaskedMerge(): improve readability.Roman Lebedev2018-05-051-4/+4
| | | | llvm-svn: 331588
* Fix a bunch of places where operator-> was used directly on the return from ↵Craig Topper2018-05-053-4/+4
| | | | | | | | | | dyn_cast. Inspired by r331508, I did a grep and found these. Mostly just change from dyn_cast to cast. Some cases also showed a dyn_cast result being converted to bool, so those I changed to isa. llvm-svn: 331577
* Mapping SDNode flags to MachineInstr flagsMichael Berg2018-05-041-1/+26
| | | | | | | | | | | | | | Summary: Providing the glue to map SDNode fast math sub flags to MachineInstr fast math sub flags. Reviewers: spatel, arsenm, wristow Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D46447 llvm-svn: 331567
* Fast Math Flag mapping into SDNodeMichael Berg2018-05-043-9/+13
| | | | | | | | | | | | | | Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage. Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar Reviewed By: spatel Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng Differential Revision: https://reviews.llvm.org/D45710 llvm-svn: 331547
* [SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCIBjorn Pettersson2018-05-042-40/+43
| | | | | | | | | | | | | | | | | | Summary: Added a helper method in RegsForValue to get a list with all the <RegNumber, RegSize> pairs that we want to iterate over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and in SelectionDAGBuilder::visitIntrinsicCall. Reviewers: vsk Reviewed By: vsk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46360 llvm-svn: 331510
* Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"Bjorn Pettersson2018-05-032-6/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This reverts SVN r331441 (reapplies r331337), together with a fix in to handle an already existing fragment expression in the dbg.value that must be fragmented due to a split PHI node. This should solve the problem seen in PR37321, which was the reason for the revert of r331337. The situation in PR37321 is that we have a PHI node like this %u.sroa = phi i80 [ %u.sroa.x, %if.x ], [ %u.sroa.y, %if.y ], [ %u.sroa.z, %if.z ] and a dbg.value like this call void @llvm.dbg.value(metadata i80 %u.sroa, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 80)) The phi node is split into three 32-bit PHI nodes %30:gr32 = PHI %11:gr32, %bb.4, %14:gr32, %bb.5, %27:gr32, %bb.8 %31:gr32 = PHI %12:gr32, %bb.4, %15:gr32, %bb.5, %28:gr32, %bb.8 %32:gr32 = PHI %13:gr32, %bb.4, %16:gr32, %bb.5, %29:gr32, %bb.8 but since the original value only is 80 bits we need to adjust the size of the last fragment expression, and with this patch we get DBG_VALUE debug-use %30:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 0, 32) DBG_VALUE debug-use %31:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 32, 32) DBG_VALUE debug-use %32:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 64, 16) Reviewers: vsk, aprantl, mstorsjo Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46384 llvm-svn: 331464
* Rename invariant.group.barrier to launder.invariant.groupPiotr Padlewski2018-05-032-2/+2
| | | | | | | | | | | | | | Summary: This is one of the initial commit of "RFC: Devirtualization v2" proposal: https://docs.google.com/document/d/16GVtCpzK8sIHNc2qZz6RN8amICNBtvjWUod2SujZVEo/edit?usp=sharing Reviewers: rsmith, amharc, kuhar, sanjoy Subscribers: arsenm, nhaehnle, javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45111 llvm-svn: 331448
* Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"Martin Storsjo2018-05-032-36/+6
| | | | | | | This reverts SVN r331337, see PR37321 for details on the regression it introduced. llvm-svn: 331441
* [SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)Bjorn Pettersson2018-05-022-6/+36
| | | | | | | | | | | | | | | | | | | | | Summary: This is a follow up to rL331182. A PHI node can be split up into several MIR PHI nodes when being selected. When there is a dbg.value intrinsic that uses the result of such a PHI node we need to select several DBG_VALUE instructions, with fragment expressions, in order to do a correct selection. Reviewers: rnk, aprantl, vsk Reviewed By: vsk Subscribers: mattd, llvm-commits, JDevlieghere, aprantl, gbedwell, rnk Tags: #debug-info Differential Revision: https://reviews.llvm.org/D46329 llvm-svn: 331337
* [DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)Vedant Kumar2018-05-011-33/+35
| | | | | | | | | | | | | | | | The logic for this combine is almost identical to the logic for a (sext (sextload x)) combine. This commit factors out the logic so it can be shared by both combines, and corrects the SDLoc assigned in the zext version of the combine. Prior to this patch, for the given test case, we would apply the location associated with the udiv instruction to instructions which perform the load. Part of: llvm.org/PR37262 llvm-svn: 331303
* [DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N)Vedant Kumar2018-05-011-3/+3
| | | | | | | | | | | | Prior to this patch, for the given test case, we would apply the location associated with the sdiv instruction to instructions which perform the load. Part of: llvm.org/PR37262. Differential Revision: https://reviews.llvm.org/D46222 llvm-svn: 331302
* [DAGCombiner] Change the SDLoc on split extloads (2/N)Vedant Kumar2018-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | In DAGCombiner, we try to simplify this pattern: ([s|z]ext (load ...)) Conceptually, a new extload which is created while splitting the load should have the same debug location as the load. Making this change affects the IROrder of the new load, causing some test case churn. In practice, the new location is never different from the location of the [s|z]ext, at least not during check-llvm or a stage2 build. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46156 llvm-svn: 331301
* [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)Vedant Kumar2018-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | Setting the right SDLoc on a newly-created zextload fixes a line table bug which resulted in non-linear stepping behavior. Several backend tests contained CHECK lines which relied on the IROrder inherited from the wrong SDLoc. This patch breaks that dependence where feasbile and regenerates test cases where not. In some cases, changing a node's IROrder may alter register allocation and spill behavior. This can affect performance. I have chosen not to prevent this by applying a "known good" IROrder to SDLocs, as this may hide a more general bug in the scheduler, or cause regressions on other test inputs. rdar://33755881, Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D45995 llvm-svn: 331300
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-018-59/+59
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [DAGCombiner] rename function attribute for disabling ftrunc transformSanjay Patel2018-04-301-2/+2
| | | | | | | | | | This is the matching name change for the Clang patch at: D46236 rL331209 Differential Revision: https://reviews.llvm.org/D46237 llvm-svn: 331210
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-303-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See r331124 for how I made a list of files missing the include. I then ran this Python script: for f in open('filelist.txt'): f = f.strip() fl = open(f).readlines() found = False for i in xrange(len(fl)): p = '#include "llvm/' if not fl[i].startswith(p): continue if fl[i][len(p):] > 'Config': fl.insert(i, '#include "llvm/Config/llvm-config.h"\n') found = True break if not found: print 'not found', f else: open(f, 'w').write(''.join(fl)) and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p` and tried to fix include ordering and whatnot. No intended behavior change. llvm-svn: 331184
* [SelectionDAG] Improve selection of DBG_VALUE using a PHI node resultBjorn Pettersson2018-04-304-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When building the selection DAG at ISel all PHI nodes are selected and lowered to Machine Instruction PHI nodes before we start to create any SDNodes. So there are no SDNodes for values produced by the PHI nodes. In the past when selecting a dbg.value intrinsic that uses the value produced by a PHI node we have been handling such dbg.value intrinsics as "dangling debug info". I.e. we have not created a SDDbgValue node directly, because there is no existing SDNode for the PHI result, instead we deferred the creationg of a SDDbgValue until we found the first use of the PHI result. The old solution had a couple of flaws. The position of the selected DBG_VALUE instruction would end up quite late in a basic block, and for example not directly after the PHI node as in the LLVM IR input. And in case there were no use at all in the basic block the dbg.value could be dropped completely. This patch introduces a new VREG kind of SDDbgValue nodes. It is similar to a SDNODE kind of node, but it refers directly to a virtual register and not a SDNode. When we do selection for a dbg.value that is using the result of a PHI node we can do a lookup of the virtual register directly (as it already is determined for the PHI node) and create a SDDbgValue node immediately instead of delaying the selection until we find a use. This should fix a problem with losing debug info at ISel as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234). It does not resolve PR37234 completely, because the debug info is dropped later on in the BranchFolder (see D46184). Reviewers: #debug-info, aprantl Reviewed By: #debug-info, aprantl Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46129 llvm-svn: 331182
* [DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisorHeejin Ahn2018-04-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector dividers. But when there is a 1 in a vector, the instruction sequence to be generated involves shifting a value by the number of its bit widths, which is undefined (https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006). Especially, in architectures that do not support vector instructions, each of element in a vector will be computed separately using scalar operations, and then the resulting value will be undef for '1' values in a vector. (All 1's vector is fine; only vectors mixed with 1 and others will be affected.) Reviewers: RKSimon, jgravelle-google Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46161 llvm-svn: 331092
* [FastISel] Actually enable local value sinking by defaultReid Kleckner2018-04-271-4/+2
| | | | llvm-svn: 331088
* [FastISel] Fix local value sinking algorithmic complexityReid Kleckner2018-04-271-3/+12
| | | | | | | | | | Now local value sinking only scans and numbers instructions added between the current flush point and the last flush point. This ensures that ISel is overall linear in the size of the BB. Fixes PR37010 and re-enables local value sinking by default. llvm-svn: 331087
* DAG: Fix not legalizing vector fcanonicalizesMatt Arsenault2018-04-261-0/+1
| | | | | | If an fcanoncialize was done on a vector type that was legal, llvm-svn: 330981
* [DAGCombiner] limit ftrunc optimizations with function attributeSanjay Patel2018-04-261-0/+8
| | | | | | | | | | As noted, the attribute name is subject to change once we have the clang side implemented, but it's clear that we need some kind of attribute-based predication here based on the discussion for: rL330437 llvm-svn: 330951
* [DAGCombiner] refactor FP->int->FP folds; NFCSanjay Patel2018-04-261-16/+26
| | | | | | | | | | | | As discussed in the post-review comments for rL330437, we need to guard this fold to allow existing code to keep working with the undefined behavior that they've come to rely on. That would mean duplicating more code than we already have, so let's fix that first. llvm-svn: 330947
* [DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legalCraig Topper2018-04-241-8/+4
| | | | | | | | | | | | We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets. Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue. This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here. Differential Revision: https://reviews.llvm.org/D45585#inline-402825 llvm-svn: 330781
* [DAGCombiner] Unfold scalar masked merge if profitableRoman Lebedev2018-04-231-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]]. [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly. Previously, `andl`+`andn`/`andps`+`andnps` / `bic`/`bsl` would be generated. (see `@out`) Now, they would no longer be generated (see `@in`). So we need to make sure that they are still generated. If the mask is constant, we do nothing. InstCombine should have unfolded it. Else, i use `hasAndNot()` TLI hook. For now, only handle scalars. https://rise4fun.com/Alive/bO6 ---- I *really* don't like the code i wrote in `DAGCombiner::unfoldMaskedMerge()`. It is super fragile. Is there something like IR Pattern Matchers for this? Reviewers: spatel, craig.topper, RKSimon, javed.absar Reviewed By: spatel Subscribers: andreadb, courbet, kristof.beyls, javed.absar, rengolin, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D45733 llvm-svn: 330646
* [SelectionDAG] Dump debug locs in SDNodesVedant Kumar2018-04-231-0/+4
| | | | | | | | | This helps debug issues where selection-dag assigns the wrong location to an instruction. Differential Revision: https://reviews.llvm.org/D45913 llvm-svn: 330618
* [SelectionDAG] Refactor lowering of atomic memory intrinsics.Daniel Neilson2018-04-232-91/+150
| | | | | | | | | | | Summary: This just refactors the lowering of the atomic memory intrinsics to more closely match the code patterns used in the lowering of the non-atomic memory intrinsics. Specifically, we encapsulate the lowering in SelectionDAG::getAtomicMem*() functions rather than embedding the code directly in the SelectionDAGBuilder code. llvm-svn: 330603
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