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* [WebAssembly] Add WasmEHFuncInfo for unwind destination informationHeejin Ahn2018-06-191-19/+42
| | | | | | | | | | | | | | | Summary: Add WasmEHFuncInfo and routines to calculate and fill in this struct to keep track of unwind destination information. This will be used in other EH related passes. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D48263 llvm-svn: 335005
* Utilize new SDNode flag functionality to expand current support for faddMichael Berg2018-06-182-29/+15
| | | | | | | | | | | | | | Summary: This patch originated from D46562 and is a proper subset, with some issues addressed. Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar Reviewed By: spatel Subscribers: wdng, nhaehnle Differential Revision: https://reviews.llvm.org/D47909 llvm-svn: 334996
* refactor of visitFADD for AllowNewConst casesMichael Berg2018-06-181-17/+20
| | | | | | | | | | | | | | Summary: Refactoring for all constant cases which require AllowNewConst and some staging for future fmf usage. Reviewers: spatel, hfinkel, wristow Reviewed By: spatel Subscribers: nhaehnle Differential Revision: https://reviews.llvm.org/D48289 llvm-svn: 334984
* Avoid needing to walk out legalization tables. NFCI.Nirav Dave2018-06-162-193/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Relanding after fixing expensive check from modifying tables. To avoid redundant work, during DAG legalization we keep tables mapping pre-legalized SDValues to post-legalized SDValues and a SDValue-to-SDValue map to enable fast node replacements. However, as the keys are nodes which may be reused it is possible that an entry in a table refers to a now deleted node N (that should have been renamed by the value replacement map) while a new node N' exists. If N' is then replaced that entry would be wrong. Previously we avoided this by when potentially violating this property, walking every table and updating all node pointers. This is very expensive but hopefully rare occurance. This patch assigns each instance of a SDValue used in legalization a unique id and uses these ids in the legalization tables. This avoids any such aliasing issue, avoiding the full table search and allowing more aggressive incremental table pruning. In some cases this is a 1000x speedup to compilation. Reviewers: jyknight, echristo, bogner, tra Reviewed By: bogner Subscribers: dberris, grandinj, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D47959 llvm-svn: 334880
* Utilize new SDNode flag functionality to expand current support for fmaMichael Berg2018-06-161-18/+14
| | | | | | | | | | | | | | Summary: This patch originated from D47388 and is a proper subset of the originating changes, containing only the fmf optimization guard extensions. Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar, rampitec, nhaehnle, nemanjai Reviewed By: rampitec, nhaehnle Subscribers: tpr, nemanjai, wdng Differential Revision: https://reviews.llvm.org/D47918 llvm-svn: 334876
* Revert r334729 "[DAG] Avoid needing to walk out legalization tables. NFCI."Francis Visoiu Mistrih2018-06-152-155/+193
| | | | | | This reverts commit r334729. llvm-svn: 334869
* Revert r334731 "Avoid unused variable in non-assert builds."Francis Visoiu Mistrih2018-06-151-1/+0
| | | | | | | | This reverts commit r334731. It breaks EXPENSIVE_CHECKS bots. llvm-svn: 334868
* [FPEnv] Expand constrained FP POWICameron McInally2018-06-152-4/+22
| | | | | | | | | | | | Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
* Utilize new SDNode flag functionality to expand current support for fdivMichael Berg2018-06-151-1/+1
| | | | | | | | | | | | | | Summary: This patch originated from D46562 and is a proper subset, with some issues addressed. Reviewers: spatel, hfinkel, wristow, arsenm Reviewed By: spatel Subscribers: wdng, nhaehnle Differential Revision: https://reviews.llvm.org/D47954 llvm-svn: 334862
* DAG: Fix creating concat_vectors with illegal typeMatt Arsenault2018-06-151-3/+6
| | | | | | | Test passes as is, but fails with future patch to make v4i16/v4f16 legal. llvm-svn: 334823
* easing the constraint for isNegatibleForFree and GetNegatedExpressionMichael Berg2018-06-141-4/+0
| | | | | | | | | | | | | | | | | Summary: Here we relax the old constraint which utilized unsafe with the TargetOption flag HonorSignDependentRoundingFPMathOption, with the assertion that unsafe is no longer needed or never was required for correctness on FDIV/FMUL. Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar Reviewed By: spatel Subscribers: efriedma, wdng, tpr Differential Revision: https://reviews.llvm.org/D48057 llvm-svn: 334769
* updating isNegatibleForFree and GetNegatedExpression with fmf for faddMichael Berg2018-06-141-4/+3
| | | | | | | | | | | | | | Summary: A FMF constraint is added to FADD with unsafe still available as the fallback Reviewers: spatel, wristow, arsenm, hfinkel Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D48180 llvm-svn: 334753
* Avoid unused variable in non-assert builds.Nirav Dave2018-06-141-0/+1
| | | | llvm-svn: 334731
* [DAG] Avoid needing to walk out legalization tables. NFCI.Nirav Dave2018-06-142-193/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid redundant work, during DAG legalization we keep tables mapping pre-legalized SDValues to post-legalized SDValues and a SDValue-to-SDValue map to enable fast node replacements. However, as the keys are nodes which may be reused it is possible that an entry in a table refers to a now deleted node N (that should have been renamed by the value replacement map) while a new node N' exists. If N' is then replaced that entry would be wrong. Previously we avoided this by when potentially violating this property, walking every table and updating all node pointers. This is very expensive but hopefully rare occurance. This patch assigns each instance of a SDValue used in legalization a unique id and uses these ids in the legalization tables. This avoids any such aliasing issue, avoiding the full table search and allowing more aggressive incremental table pruning. In some cases this is a 1000x speedup to compilation. Reviewers: jyknight, echristo, bogner, tra Reviewed By: bogner Subscribers: dberris, grandinj, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D47959 llvm-svn: 334729
* [DAGCombiner] remove hasOneUse() check from fadd constants transformSanjay Patel2018-06-131-7/+6
| | | | | | | | | | | We're constant folding here, so we shouldn't check uses. This matches the IR optimizer behavior. The x86 test shows the expected win. The AArch64 test shows something else. This only seems to happen if the "generic" AArch64 CPU model is used by MachineCombiner, so I'll file a bug report to follow-up. llvm-svn: 334608
* [FPEnv] Expand constrained FP operationsCameron McInally2018-06-131-8/+88
| | | | | | | | | | Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
* [DAGCombiner] Recognize more patterns for ABSKrzysztof Parzyszek2018-06-121-7/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D47831 llvm-svn: 334553
* Utilize new SDNode flag functionality to expand current support for fmulMichael Berg2018-06-121-2/+5
| | | | | | | | | | | | | | Summary: This patch originated from D46562 and is a proper subset, with some issues addressed for fmul. Reviewers: spatel, hfinkel, wristow, arsenm Reviewed By: spatel Subscribers: nhaehnle, wdng Differential Revision: https://reviews.llvm.org/D47911 llvm-svn: 334514
* [SelectionDAG] Provide default expansion for rotatesKrzysztof Parzyszek2018-06-122-2/+52
| | | | | | | | | | | | | Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
* DAG: Fix extract_subvector combine for a single elementMatt Arsenault2018-06-111-3/+12
| | | | | | | | | | | | | | | | This would fail before because 1x vectors aren't legal, so instead just use the scalar type. Avoids regressions in a future AMDGPU commit to add v4i16/v4f16 as legal types. Test update is just the one test that this triggers on in tree now. It wasn't checking anything before. The result is completely changed since the selects are eliminated. Not sure if it's considered better or not. llvm-svn: 334440
* [DAGCombiner] match vector compare and select sizes with extload operand ↵Sanjay Patel2018-06-101-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (PR37427) This patch started off much more general and ambitious, but it's been a nightmare seeing all the ways x86 vector codegen can go wrong. So the code is still structured to allow extending easily, but it's currently limited in several ways: 1. Only handle cases with an extending load. 2. Only handle cases with a zero constant compare. 3. Ignore setcc with vector bitmask (SetCCWidth != 1) - so AVX512 should be unaffected. The motivating case from PR37427: https://bugs.llvm.org/show_bug.cgi?id=37427 ...is the 1st test, and that shows the expected win - we eliminated the unnecessary intermediate cast. There's a clear regression in the last test (sgt_zero_fp_select) because we longer recognize a 'SHRUNKBLEND' opportunity. I think that general problem is also present in sgt_zero, so I'll try to fix that in a follow-up. We need to match a sign-bit setcc from a sign-extended operand and remove it. Differential Revision: https://reviews.llvm.org/D47330 llvm-svn: 334378
* Use SmallPtrSet instead of SmallSet in places where we iterate over the set.Craig Topper2018-06-091-1/+1
| | | | | | | | SmallSet forwards to SmallPtrSet for pointer types. SmallPtrSet supports iteration, but a normal SmallSet doesn't. So if it wasn't for the forwarding, this wouldn't work. These places were found by hiding the begin/end methods in the SmallSet forwarding llvm-svn: 334343
* [DAGCombiner] clean up comments; NFCSanjay Patel2018-06-081-8/+5
| | | | llvm-svn: 334312
* Utilize new SDNode flag functionality to expand current support for fsubMichael Berg2018-06-081-17/+23
| | | | | | | | | | | | | | Summary: This patch originated from D46562 and is a proper subset, with some issues addressed for fsub. Reviewers: spatel, hfinkel, wristow, arsenm Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D47910 llvm-svn: 334306
* [DAGCombine] Fix for PR37667Sam Parker2018-06-081-0/+16
| | | | | | | | | | While trying to propagate AND masks back to loads, we currently allow one non-load node to be included as a leaf in chain. This fix now limits that node to produce only a single data value. Differential Revision: https://reviews.llvm.org/D47878 llvm-svn: 334268
* propagate fast math flags via IR on fma and sub expressionsMichael Berg2018-06-072-47/+56
| | | | | | | | | | | | | | Summary: This change uses fmf subflags to guard fma optimizations as well as unsafe. These changes originated from D46483 and have been simplified via getNode. Reviewers: spatel, arsenm, hfinkel, javed.absar Reviewed By: spatel Subscribers: nemanjai, wdng Differential Revision: https://reviews.llvm.org/D47388 llvm-svn: 334242
* DAG: Avoid bitcast/ext/build_vector combineMatt Arsenault2018-06-071-1/+4
| | | | | | | | | | | | | | | | | | | | | This avoids regressions in a future AMDGPU change to make v4i16/v4f16 legal. For these types, build_vector is implemented as bitcasted operations on v2i32. This combine was creating v4i16s out of what would have been already been a v2i32 build_vector, creating a mess of nodes that never get cleaned up. I'm not sure this is the right condition to check. I initially tried just checking for the legality of the new build_vector. This works for my case, but breaks dozens of x86 tests. A Mips test seems to show some improvement or at least a neutral change. I don't want to think about how long it would take to analyze the set of different x86 vector operations impacted. Test included in future commit. llvm-svn: 334218
* guard fsqrt with fmf sub flagsMichael Berg2018-06-061-5/+4
| | | | | | | | | | | | | | | | | Summary: This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483. It contains only context for fsqrt. Reviewers: spatel, hfinkel, arsenm Reviewed By: spatel Subscribers: hfinkel, wdng, andrew.w.kaylor, wristow, efriedma, nemanjai Differential Revision: https://reviews.llvm.org/D47749 llvm-svn: 334113
* guard fneg with fmf sub flagsMichael Berg2018-06-051-3/+3
| | | | | | | | | | | | | | Summary: This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483. Reviewers: spatel, hfinkel Reviewed By: spatel Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D47389 llvm-svn: 334037
* DAG: Stop dropping invariant/dereferencableMatt Arsenault2018-06-051-4/+3
| | | | | | | | | | | | | When legalizing illegal FP load results, this was for some reason dropping the invariant and dereferencable memory flags. There doesn't seem to be any reason for this, and the equivalent isn't done for integer loads. Fixes an issue in a future AMDGPU commit where some identical loads fail to merge because one of the loads ends up dropping the flags. llvm-svn: 334020
* Fix -Wcovered-switch-default warning and clang-format itReid Kleckner2018-06-041-10/+8
| | | | llvm-svn: 333967
* [CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperandsScott Linder2018-06-041-0/+2
| | | | | | | | Some overloads failed to update divergence. Differential Revision: https://reviews.llvm.org/D47148 llvm-svn: 333947
* [DAGcombine] Teach the combiner about -a = ~a + 1Amaury Sechet2018-06-041-1/+60
| | | | | | | | | | | | Summary: This include variant for add, uaddo and addcarry. usubo and subcarry require the carry to be flipped to preserve semantic, but we chose to do the transform anyway in that case as to push the transform down the carry chain. Reviewers: efriedma, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46505 llvm-svn: 333943
* Get rid of SETCCEAmaury Sechet2018-06-045-52/+12
| | | | | | | | | | | | Summary: It has been deprecated in favor of SETCCCARRY for a year now and isn't used by any in tree backend. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47685 llvm-svn: 333939
* [SelectionDAG] Add missing closing parentheses in comments, NFCKrzysztof Parzyszek2018-06-041-6/+6
| | | | llvm-svn: 333907
* [DAG] Avoid checking for consecutive stores in store merge. NFCI.Nirav Dave2018-06-011-319/+340
| | | | llvm-svn: 333766
* [DAG] Simplify Expression. NFC.Nirav Dave2018-06-011-9/+3
| | | | llvm-svn: 333765
* [DAG] Remove untriggerable check. NFCI.Nirav Dave2018-06-011-10/+0
| | | | | | Candidate check precludes this check. llvm-svn: 333764
* [DAG] Prune store merge legal store check to stop invalid size. NFCI.Nirav Dave2018-06-011-0/+15
| | | | | | Do not consider store sizes large than the maximum legal store size. llvm-svn: 333763
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-012-9/+25
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* [WebAssembly] Support instruction selection for catching exceptionsHeejin Ahn2018-05-311-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This lowers exception catching-related instructions: 1. Lowers `wasm.catch` intrinsic to `catch` instruction 2. Removes `catchpad` and `cleanuppad` instructions; they are not necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or `MachineBasicBlock::isEHPad()` can be used instead.) 3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret` and `cleanupret` instructions in isel, which will be replaced with other instructions in `WebAssemblyExceptionPrepare` pass. 4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various transformation for EH. Currently this pass only replaces `catchret` and `cleanupret` instructions into appropriate wasm instructions to make this patch successfully run until the end. Currently this does not handle lowering of intrinsics related to LSDA info generation (`wasm.landingpad.index` and `wasm.lsda`), because they cannot be tested without implementing `EHStreamer`'s wasm-specific handlers. They are marked as TODO, which is needed to make isel pass. Also this does not generate `try` and `end_try` markers yet, which will be handled in later patches. This patch is based on the first wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D44090 llvm-svn: 333705
* DAG: Remove redundant version of getRegisterTypeForCallingConvMatt Arsenault2018-05-291-4/+4
| | | | | | | | | | | There seems to be no real reason to have these separate copies. The existing implementations just copy each other for x86. For Mips there is a subtle difference, which is just a bug since it changes based on the context where which one was called. Dropping this version, all tests pass. If I try to merge them to match the removed version, a test fails. llvm-svn: 333440
* [StrictFP] Make getStrictFPOpcodeAction(...) more accessibleCameron McInally2018-05-291-32/+2
| | | | | | | | NFCI. This function will be reused in upcoming patches. Differential Revision: https://reviews.llvm.org/D47380 llvm-svn: 333433
* [WebAssembly] Add functions for EHScopesHeejin Ahn2018-05-232-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There are functions using the term 'funclet' to refer to both 1. an EH scopes, the structure of BBs that starts with catchpad/cleanuppad and ends with catchret/cleanupret, and 2. a small function that gets outlined in AsmPrinter, which is the original meaning of 'funclet'. So far the two have been the same thing; EH scopes are always outlined in AsmPrinter as funclets at the end of the compilation pipeline. But now wasm also uses scope-based EH but does not outline those, so we now need to correctly distinguish those two use cases in functions. This patch splits `MachineBasicBlock::isFuncletEntry` into `isFuncletEntry` and `isEHScopeEntry`, and `MachineFunction::hasFunclets` into `hasFunclets` and `hasEHScopes`, in order to distinguish the two different use cases. And this also changes some uses of the term 'funclet' to 'scope' in `getFuncletMembership` and change the function name to `getEHScopeMembership` because this function is not about outlined funclets but about EH scope memberships. This change is in the same vein as D45559. Reviewers: majnemer, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D47005 llvm-svn: 333045
* [DAG] fold FP binops with undef operands to NaNSanjay Patel2018-05-211-11/+12
| | | | | | | | | | | | | | | | | | This is the FP sibling of D43141 with the corresponding IR change in rL327212. We can't propagate undef here because if a variable operand is a NaN, these binops must propagate NaN. Neither global nor node-level fast-math makes a difference. If we have 'nnan', I think later folds can turn the NaN into undef. The tests in X86/fp-undef.ll are meant to be the definitive verification for these folds - everything reduces identically now. The other test changes are collateral damage. They may need to be altered to preserve their intent. Differential Revision: https://reviews.llvm.org/D47026 llvm-svn: 332920
* [DAGCombiner] isAllOnesConstantOrAllOnesSplatConstant(): look through bitcastsRoman Lebedev2018-05-211-6/+9
| | | | | | | | | | | | Summary: As pointed out in D46528, we errneously transform cases like `xor X, -1`, even though we use said function. It's because the `-1` is actually a bitcast there. So i think we can just look through it in the function. Differential Revision: https://reviews.llvm.org/D47156 llvm-svn: 332905
* [DAGCombine][X86][AArch64] Masked merge unfolding: vector edition.Roman Lebedev2018-05-211-4/+0
| | | | | | | | | | | | | | | Summary: This **appears** to be the last missing piece for the masked merge pattern handling in the backend. This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]]. [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly. Previously, `andps`+`andnps` / `bsl` would be generated. (see `@out`) Now, they would no longer be generated (see `@in`), and we need to make sure that they are generated. Differential Revision: https://reviews.llvm.org/D46528 llvm-svn: 332904
* [DAGCombiner] Use computeKnownBits to match rotate patterns that have had ↵Craig Topper2018-05-211-7/+18
| | | | | | | | | | | | | | | | their amount masking modified by simplifyDemandedBits SimplifyDemandedBits can remove bits from the masks for the shift amounts we need to see to detect rotates. This patch uses zeroes from computeKnownBits to fill in some of these mask bits to make the match work. As currently written this calls computeKnownBits even when the mask hasn't been simplified because it made the code simpler. If we're worried about compile time performance we can improve this. I know we're talking about making a rotate intrinsic, but hopefully we can go ahead and do this change and just make sure the rotate intrinsic also handles it. Differential Revision: https://reviews.llvm.org/D47116 llvm-svn: 332895
* DAG: Fix crash on shift with large shift amountsMatt Arsenault2018-05-181-2/+2
| | | | | | Fixes bug 37521. llvm-svn: 332774
* [DAG] Prune cycle check in store merge.Nirav Dave2018-05-161-18/+54
| | | | | | | | | | | | | | | | | | | | As part of merging stores we check that fusing the nodes does not cause a cycle due to one candidate store being indirectly dependent on another store (this may happen via chained memory copies). This is done by searching if a store is a predecessor to another store's value. Prune the search at the candidate search's root node which is a predecessor to all candidate stores. This reduces the size of the subgraph searched in large basic blocks. Reviewers: jyknight Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D46955 llvm-svn: 332490
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