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* Convert MaskedValueIsZero and all its users to use APInt. Also addDan Gohman2008-02-251-8/+16
| | | | | | a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
* In TargetLowering::LowerCallTo, don't assert thatDuncan Sands2008-02-141-2/+2
| | | | | | | | | | | | | | | | | the return value is zero-extended if it isn't sign-extended. It may also be any-extended. Also, if a floating point value was returned in a larger floating point type, pass 1 as the second operand to FP_ROUND, which tells it that all the precision is in the original type. I think this is right but I could be wrong. Finally, when doing libcalls, set isZExt on a parameter if it is "unsigned". Currently isSExt is set when signed, and nothing is set otherwise. This should be right for all calls to standard library routines. llvm-svn: 47122
* Change how FP immediates are handled. Nate Begeman2008-02-141-0/+7
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBitsDan Gohman2008-02-131-3/+2
| | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096
* Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.Dan Gohman2008-02-131-3/+3
| | | | | | | Add an overload that supports the uint64_t interface for use by clients that haven't been updated yet. llvm-svn: 47039
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-3/+3
| | | | llvm-svn: 46930
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-1/+1
| | | | | | | | and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. llvm-svn: 46538
* Handle 'X' constraint in asm's better.Dale Johannesen2008-01-291-0/+13
| | | | llvm-svn: 46485
* Forgot these.Evan Cheng2008-01-241-0/+6
| | | | llvm-svn: 46292
* remove extraneous &'s.Chris Lattner2008-01-181-2/+2
| | | | llvm-svn: 46171
* This commit changes:Chris Lattner2008-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret llvm-svn: 46140
* Add support for targets that have a legal ISD::TRAP.Chris Lattner2008-01-151-0/+3
| | | | llvm-svn: 46014
* Output sinl for a long double FSIN node, not sin.Duncan Sands2008-01-101-2/+9
| | | | | | | | Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
* fix typo duncan noticed!Chris Lattner2007-12-301-1/+1
| | | | llvm-svn: 45459
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Fold comparisons against a constant nan, and optimize ORD/UNORD Chris Lattner2007-12-291-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | comparisons with a constant. This allows us to compile isnan to: _foo: fcmpu cr7, f1, f1 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr instead of: LCPI1_0: ; float .space 4 _foo: lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr7, f1, f0 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr llvm-svn: 45405
* initial code for forming an FGETSIGN node. This is disabled untilChris Lattner2007-12-221-0/+26
| | | | | | legalizer support goes in. llvm-svn: 45323
* Add a new FGETSIGN operation, which defaults to expand on allChris Lattner2007-12-221-1/+5
| | | | | | targets. llvm-svn: 45320
* Support returning non-power-of-2 vectors to unblock some workNate Begeman2007-11-271-0/+7
| | | | llvm-svn: 44371
* Much improved pic jumptable codegen:Evan Cheng2007-11-091-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Then: call "L1$pb" "L1$pb": popl %eax ... LBB1_1: # entry imull $4, %ecx, %ecx leal LJTI1_0-"L1$pb"(%eax), %edx addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx jmpl *%edx .align 2 .set L1_0_set_3,LBB1_3-LJTI1_0 .set L1_0_set_2,LBB1_2-LJTI1_0 .set L1_0_set_5,LBB1_5-LJTI1_0 .set L1_0_set_4,LBB1_4-LJTI1_0 LJTI1_0: .long L1_0_set_3 .long L1_0_set_2 Now: call "L1$pb" "L1$pb": popl %eax ... LBB1_1: # entry addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax jmpl *%eax .align 2 .set L1_0_set_3,LBB1_3-"L1$pb" .set L1_0_set_2,LBB1_2-"L1$pb" .set L1_0_set_5,LBB1_5-"L1$pb" .set L1_0_set_4,LBB1_4-"L1$pb" LJTI1_0: .long L1_0_set_3 .long L1_0_set_2 llvm-svn: 43924
* Didn't mean to check these in.Evan Cheng2007-11-091-7/+0
| | | | llvm-svn: 43923
* Bug fix. Passive nodes are not in SUnitMap.Evan Cheng2007-11-091-0/+7
| | | | llvm-svn: 43922
* Move the LowerMEMCPY and LowerMEMCPYCall to a common place.Rafael Espindola2007-11-051-0/+55
| | | | | | Thanks for the suggestions Bill :-) llvm-svn: 43742
* Make labels work in asm blocks; allow labels asDale Johannesen2007-11-051-2/+7
| | | | | | | parameters. Rename ValueRefList to ParamList in AsmParser, since its only use is for parameters. llvm-svn: 43734
* Add runtime library names for pow.Dan Gohman2007-10-111-0/+4
| | | | llvm-svn: 42880
* Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} toDan Gohman2007-10-081-8/+20
| | | | | | | | use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. llvm-svn: 42762
* First round of ppc long double. call/return andDale Johannesen2007-10-051-6/+24
| | | | | | | | | basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
* Add sqrt and powi intrinsics for long double.Dale Johannesen2007-09-281-0/+2
| | | | llvm-svn: 42423
* Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) andDan Gohman2007-09-251-0/+5
| | | | | | | the check to see if the assembler supports .loc from X86TargetLowering into the superclass TargetLowering. llvm-svn: 42297
* initialize SetCCResultContents, fixing PR1693Chris Lattner2007-09-211-0/+1
| | | | llvm-svn: 42193
* More long double fixes. x86_64 should build now.Dale Johannesen2007-09-191-0/+4
| | | | llvm-svn: 42155
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-2/+2
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* rename isOperandValidForConstraint to LowerAsmOperandForConstraint, Chris Lattner2007-08-251-11/+13
| | | | | | changing the interface to allow for future changes. llvm-svn: 41384
* long double 9 of N. This finishes up the X86-32 bitsDale Johannesen2007-08-091-0/+1
| | | | | | | | (constants are still not handled). Adds ConvertActions to control fp-to-fp conversions (these are currently defaulted for all other targets, so no changes there). llvm-svn: 40958
* Initialize the IndexedModeActions array with memset beforeDan Gohman2007-07-091-1/+3
| | | | | | | | | | | updating it with calls to setIndexedLoadAction/setIndexedStoreAction, which only update a few bits at a time. This avoids ostensible undefined behavior of operationg on values which may be trap-representations, and as a practical matter fixes errors from valgrind, which doesn't track uninitialized memory with bit granularity. llvm-svn: 38468
* Add new TargetLowering code to provide the final register type that anDan Gohman2007-06-281-95/+67
| | | | | | | | | | | | illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
* Generalize MVT::ValueType and associated functions to be able to representDan Gohman2007-06-251-23/+29
| | | | | | | | | | | | | | | extended vector types. Remove the special SDNode opcodes used for pre-legalize vector operations, and the special MVT::Vector type used with them. Adjust lowering and legalize to work with the normal SDNode kinds instead, and to use the normal MVT functions to work with vector types instead of using the two special operands that the pre-legalize nodes held. This allows pre-legalize and post-legalize DAGs, and the code that operates on them, to be more consistent. Pre-legalize vector operators can be handled more consistently with scalar operators. And, -view-dag-combine1-dags and -view-legalize-dags now look prettier for vector code. llvm-svn: 37719
* Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits fromDan Gohman2007-06-221-553/+8
| | | | | | | | | TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. llvm-svn: 37704
* Tidy up ValueType names in comments.Dan Gohman2007-06-211-3/+3
| | | | llvm-svn: 37688
* Rename TargetLowering::getNumElements and friends toDan Gohman2007-06-211-5/+5
| | | | | | | TargetLowering::getNumRegisters and similar, to avoid confusion with the actual number of elements for vector types. llvm-svn: 37687
* Fix CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll, and PR1473.Chris Lattner2007-05-301-1/+1
| | | | llvm-svn: 37362
* same patch as the previous one, but the symmetric caseChris Lattner2007-05-191-1/+1
| | | | llvm-svn: 37249
* Disable the (A == (B-A)) -> 2*A == B xform when the sub has multiple uses (inChris Lattner2007-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | this case, the xform introduces an extra operation). This compiles PowerPC/compare-duplicate.ll into: _test: subf r2, r3, r4 cmplw cr0, r2, r3 bne cr0, LBB1_2 ;F instead of: _test: slwi r2, r3, 1 subf r3, r3, r4 cmplw cr0, r4, r2 bne cr0, LBB1_2 ;F This is target independent of course. llvm-svn: 37246
* Qualify several calls to functions in the MVT namespace, for consistency.Dan Gohman2007-05-181-2/+2
| | | | llvm-svn: 37230
* disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits forChris Lattner2007-05-171-0/+13
| | | | | | | i128 integers. The 64-bit masks are not wide enough to represent the results. These should be converted to APInt someday. llvm-svn: 37169
* Add target hook to specify block size limit for if-conversion.Evan Cheng2007-05-161-0/+1
| | | | llvm-svn: 37134
* Allow i/s to match (gv+c). This fixes ↵Chris Lattner2007-05-031-10/+31
| | | | | | | | CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll and PR1382 llvm-svn: 36672
* fix a pastoChris Lattner2007-04-181-1/+1
| | | | llvm-svn: 36242
* Fix a bug in my previous patch, grabbing the shift amount width from theChris Lattner2007-04-171-2/+2
| | | | | | wrong operand. llvm-svn: 36223
* Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.Chris Lattner2007-04-171-5/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
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