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* Get rid of the non-DebugLoc-ified getNOT() method.Bill Wendling2009-01-301-5/+5
| | | | llvm-svn: 63442
* Fix two typos that Duncan spotted in a comment.Dan Gohman2009-01-291-1/+1
| | | | llvm-svn: 63312
* Make x86's BT instruction matching more thorough, and add someDan Gohman2009-01-291-1/+42
| | | | | | | | | dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
* Make isOperationLegal do what its name suggests, and introduce aDan Gohman2009-01-281-4/+4
| | | | | | | | | | | | | | | new isOperationLegalOrCustom, which does what isOperationLegal previously did. Update a bunch of callers to use isOperationLegalOrCustom instead of isOperationLegal. In some case it wasn't obvious which behavior is desired; when in doubt I changed then to isOperationLegalOrCustom as that preserves their previous behavior. This is for the second half of PR3376. llvm-svn: 63212
* Add SelectionDAG::getNOT method to construct bitwise NOT operations,Bob Wilson2009-01-221-14/+14
| | | | | | | corresponding to the "not" and "vnot" PatFrags. Use the new method in some places where it seems appropriate. llvm-svn: 62768
* Few targets like PIC16 wants libcall generation for illegal type i16.Sanjiv Gupta2009-01-181-0/+4
| | | | llvm-svn: 62467
* Make getWidenVectorType const; this file was missed in theDan Gohman2009-01-151-1/+1
| | | | | | previous commit. llvm-svn: 62266
* TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need itsDan Gohman2009-01-051-2/+0
| | | | | | | own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END, as long as it takes care to round up when needed. llvm-svn: 61733
* Fix PR3274: when promoting the condition of a BRCOND node,Duncan Sands2009-01-011-1/+1
| | | | | | | | | | promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). llvm-svn: 61542
* Added support for vector widening.Mon P Wang2008-12-181-2/+26
| | | | llvm-svn: 61209
* Followup to r60283: optimize arbitrary width signed divisions as well Eli Friedman2008-11-301-71/+34
| | | | | | as unsigned divisions. Same caveats as before. llvm-svn: 60284
* Fix for PR2164: allow transforming arbitrary-width unsigned divides intoEli Friedman2008-11-301-95/+65
| | | | | | | | | | | multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
* APIntify a test which is potentially unsafe otherwise, and fix the Eli Friedman2008-11-301-3/+10
| | | | | | | | | nearby FIXME. I'm not sure what the right way to fix the Cell test was; if the approach I used isn't okay, please let me know. llvm-svn: 60277
* Rename SetCCResultContents to BooleanContents. InDuncan Sands2008-11-231-1/+1
| | | | | | | practice these booleans are mostly produced by SetCC, however the concept is more general. llvm-svn: 59911
* Fix the testb optimization so x86 also bootstraps.Dale Johannesen2008-11-121-3/+1
| | | | | | Reenable test. llvm-svn: 59101
* Temporarily revert r58979 and related patch. It's causing a failure in X86 ↵Bill Wendling2008-11-101-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | bootstrap: Comparing stages 2 and 3 warning: ./cc1-checksum.o differs warning: ./cc1obj-checksum.o differs warning: ./cc1objplus-checksum.o differs warning: ./cc1plus-checksum.o differs Bootstrap comparison failure! ./alias.o differs ./alloc-pool.o differs ./attribs.o differs ./bb-reorder.o differs ./bitmap.o differs ./build/errors.o differs ./build/genattrtab.o differs ./build/genautomata.o differs ./build/genemit.o differs ./build/genextract.o differs ... -bw llvm-svn: 59003
* Really fix testb optimization on big-endian.Dale Johannesen2008-11-101-5/+8
| | | | | | Fixes ppc32 bootstrap. llvm-svn: 58979
* Temporarily revert 58825, which breaks PPC bootstrap.Dale Johannesen2008-11-091-1/+3
| | | | | | xs llvm-svn: 58930
* Make testb optimization work on big-endian targets.Dale Johannesen2008-11-081-1/+4
| | | | llvm-svn: 58874
* When we're doing a compare of load-AND-constant to 0Dale Johannesen2008-11-071-0/+46
| | | | | | | | | (e.g. a bitfield test) narrow the load as much as possible. The has the potential to avoid unnecessary partial-word load-after-store conflicts, which cause stalls on several targets. Also a size win on x86 (testb vs testl). llvm-svn: 58825
* Widening cleanupMon P Wang2008-11-061-1/+1
| | | | llvm-svn: 58796
* Add initial support for vector widening. Logic is set to widen for X86.Mon P Wang2008-10-301-1/+15
| | | | | | | One will only see an effect if legalizetype is not active. Will move support to LegalizeType soon. llvm-svn: 58426
* Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman2008-10-181-0/+17
| | | | | | | | | | | | | | | | | | | | | | and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
* Keep track of *which* input constraint matches an outputChris Lattner2008-10-171-3/+3
| | | | | | | constraint. Reject asms where an output has multiple input constraints tied to it. llvm-svn: 57687
* add an assert so that PR2356 explodes instead of running off anChris Lattner2008-10-171-0/+15
| | | | | | | array. Improve some minor comments, refactor some helpers in AsmOperandInfo. No functionality change for valid code. llvm-svn: 57686
* - Add target lowering hooks that specify which setcc conditions are illegal,Evan Cheng2008-10-151-0/+1
| | | | | | | | | | | i.e. conditions that cannot be checked with a single instruction. For example, SETONE and SETUEQ on x86. - Teach legalizer to implement *illegal* setcc as a and / or of a number of legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ. - Move x86 target over. llvm-svn: 57542
* Rename LoadX to LoadExt.Evan Cheng2008-10-141-1/+1
| | | | llvm-svn: 57526
* * Make TargetLowering not crash when TargetMachine::getTargetAsmInfo() returnsMatthijs Kooijman2008-10-131-1/+2
| | | | | | | null. This assumes that any target that does not have AsmInfo, does not support "LocAndDot". llvm-svn: 57438
* Rename ConstantSDNode's getSignExtended to getSExtValue, forDan Gohman2008-09-261-3/+3
| | | | | | | consistancy with ConstantInt, and re-implement it in terms of ConstantInt's getSExtValue. llvm-svn: 56700
* Properly handle 'm' inline asm constraints. If a GV is being selected for ↵Evan Cheng2008-09-241-3/+5
| | | | | | the addressing mode, it requires the same logic for PIC relative addressing, etc. llvm-svn: 56526
* Make log, log2, log10, exp, exp2 use Expand byDale Johannesen2008-09-221-0/+12
| | | | | | default. llvm-svn: 56471
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-19/+21
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* Add intrinsics for log, log2, log10, exp, exp2.Dale Johannesen2008-09-041-0/+20
| | | | | | No functional change (and no FE change to generate them). llvm-svn: 55753
* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-281-36/+36
| | | | | | Node to reflect semantics llvm-svn: 55504
* Add libcalls for the new rounding opcodes.Dan Gohman2008-08-211-0/+20
| | | | llvm-svn: 55133
* Add the remaining fp_round libcalls:Bruno Cardoso Lopes2008-08-071-2/+15
| | | | | | | | | | | | | FPROUND_F80_F32, FPROUND_PPCF128_F32, FPROUND_F80_F64, FPROUND_PPCF128_F64 Support for soften float fp_round operands is added, Mips needs this to round f64->f32. Also added support to soften float FABS result, Mips doesn't support double fabs results while in 'single float only' mode. llvm-svn: 54484
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-54/+54
| | | | llvm-svn: 54128
* Factorize some code for determining which libcall to use.Duncan Sands2008-07-171-0/+158
| | | | llvm-svn: 53713
* It is pointless to turn a UINT_TO_FP into anDuncan Sands2008-07-111-0/+8
| | | | | | | | | SINT_TO_FP libcall plus additional operations: it might as well be a direct UINT_TO_FP libcall. So only turn it into an SINT_TO_FP if the target has special handling for SINT_TO_FP. llvm-svn: 53461
* Add two missing SINT_TO_FP libcalls.Duncan Sands2008-07-111-0/+2
| | | | llvm-svn: 53460
* Add support for 128 bit shifts and 32 bit shiftsDuncan Sands2008-07-111-0/+3
| | | | | | on 16 bit machines. llvm-svn: 53458
* Add support for 128 bit multiplicative operations.Duncan Sands2008-07-101-0/+5
| | | | | | | | | Lack of these caused a bootstrap failure with Fortran on x86-64 with LegalizeTypes turned on. While there, be nice to 16 bit machines and support expansion of i32 too. llvm-svn: 53408
* Add a mysteriously missing libcall, FPTOSINT_F80_I32.Duncan Sands2008-07-101-0/+1
| | | | | | | Be nice to 16 bit machines by supporting FP_TO_XINT expansion for these. llvm-svn: 53407
* Add support for expanding PPC 128 bit floats.Duncan Sands2008-06-251-0/+2
| | | | | | | | | | | | | | | | | | | | For this it is convenient to permit floats to be used with EXTRACT_ELEMENT, so I tweaked things to allow that. I also added libcalls for ppcf128 to i32 forms of FP_TO_XINT, since they exist in libgcc and this case can certainly occur (and does occur in the testsuite) - before the i64 libcall was being used. Also, the XINT_TO_FP result seemed to be wrong when the argument is an i128: the wrong fudge factor was added (the i32 and i64 cases were handled directly, but the i128 code fell through to some generic softening code which seemed to think it was i64 to f32!). So I fixed it by adding a fudge factor that I found in my breakfast cereal. llvm-svn: 52739
* Teach isGAPlusOffset to respect a GlobalAddressSDNode's offsetDan Gohman2008-06-091-1/+3
| | | | | | value, which is something that apparently isn't used much. llvm-svn: 52158
* Various tweaks related to apint codegen. No functionalityDuncan Sands2008-06-091-1/+1
| | | | | | change for non-funky-sized integers. llvm-svn: 52151
* Remove comparison methods for MVT. The main causeDuncan Sands2008-06-081-1/+1
| | | | | | | | | | | of apint codegen failure is the DAG combiner doing the wrong thing because it was comparing MVT's using < rather than comparing the number of bits. Removing the < method makes this mistake impossible to commit. Instead, add helper methods for comparing bits and use them. llvm-svn: 52098
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-73/+76
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Xform bitconvert(build_pair(load a, load b)) to a single load if the load ↵Evan Cheng2008-05-121-1/+1
| | | | | | locations are at the right offset from each other. llvm-svn: 51008
* Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can ↵Evan Cheng2008-05-121-0/+68
| | | | | | make use of it. llvm-svn: 50991
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