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path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-191-2/+2
| | | | | | of EVT. llvm-svn: 170532
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-191-9/+9
| | | | llvm-svn: 170524
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-191-2/+2
| | | | | | EVT. llvm-svn: 170522
* After reducing the size of an operation in the DAG we zero-extend the reducedNadav Rotem2012-12-191-2/+5
| | | | | | | | bitwidth op back to the original size. If we reduce ANDs then this can cause an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits are equal or smaller than the size of the reduced operation. llvm-svn: 170505
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-191-6/+6
| | | | | | single attribute in the future. llvm-svn: 170502
* Remove more of 'else's after 'returns'. No functional change.Craig Topper2012-12-191-6/+6
| | | | llvm-svn: 170497
* Remove a bunch of 'else's after 'returns'Craig Topper2012-12-191-18/+18
| | | | llvm-svn: 170496
* Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be ↵Craig Topper2012-12-191-3/+9
| | | | | | rewritten as a compare against a constant 0 with the opposite condition. llvm-svn: 170495
* Check multiple register classes for inline asm tied registersHal Finkel2012-12-181-3/+16
| | | | | | | | | | | | | | | | | | A register can be associated with several distinct register classes. For example, on PPC, the floating point registers are each associated with both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code would fail when provided with a floating point register and an f64 operand because it would happen to find the register in the F4RC class first and return that. From the F4RC class, SDAG would extract f32 as the register type and then assert because of the invalid implied conversion between the f64 value and the f32 register. Instead, search all register classes. If a register class containing the the requested register has the requested type, then return that register class. Otherwise, as before, return the first register class found that contains the requested register. llvm-svn: 170436
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-131-1/+1
| | | | llvm-svn: 170148
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-30/+29
| | | | llvm-svn: 169854
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-111-9/+10
| | | | | | from EVT. llvm-svn: 169849
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-111-4/+4
| | | | | | EVTs. llvm-svn: 169848
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-111-4/+4
| | | | | | EVTs. llvm-svn: 169847
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-111-2/+2
| | | | | | of EVT. llvm-svn: 169845
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-111-9/+9
| | | | llvm-svn: 169843
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-111-2/+2
| | | | | | EVT. llvm-svn: 169842
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-111-1/+1
| | | | llvm-svn: 169839
* Fix a coding style nit.Eric Christopher2012-12-101-2/+2
| | | | llvm-svn: 169776
* Replace r169459 with something safer. Rather than having computeMaskedBits toEvan Cheng2012-12-061-24/+0
| | | | | | | | | | understand target implementation of any_extend / extload, just generate zero_extend in place of any_extend for liveouts when the target knows the zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz). rdar://12771555 llvm-svn: 169536
* Let targets provide hooks that compute known zero and ones for any_extendEvan Cheng2012-12-061-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and extload's. If they are implemented as zero-extend, or implicitly zero-extend, then this can enable more demanded bits optimizations. e.g. define void @foo(i16* %ptr, i32 %a) nounwind { entry: %tmp1 = icmp ult i32 %a, 100 br i1 %tmp1, label %bb1, label %bb2 bb1: %tmp2 = load i16* %ptr, align 2 br label %bb2 bb2: %tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ] %cmp = icmp ult i16 %tmp3, 24 br i1 %cmp, label %bb3, label %exit bb3: call void @bar() nounwind br label %exit exit: ret void } This compiles to the followings before: push {lr} mov r2, #0 cmp r1, #99 bhi LBB0_2 @ BB#1: @ %bb1 ldrh r2, [r0] LBB0_2: @ %bb2 uxth r0, r2 cmp r0, #23 bhi LBB0_4 @ BB#3: @ %bb3 bl _bar LBB0_4: @ %exit pop {lr} bx lr The uxth is not needed since ldrh implicitly zero-extend the high bits. With this change it's eliminated. rdar://12771555 llvm-svn: 169459
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-11/+11
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski2012-11-291-1/+1
| | | | | | | | computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. llvm-svn: 168882
* Cleanup: Simplify loop end logic in computeRegisterProperties().Patrik Hägglund2012-11-231-5/+4
| | | | llvm-svn: 168507
* OutputArg: added an index of the original argument to match the change toManman Ren2012-11-011-1/+1
| | | | | | | | | | InputArg in r165616. This will enable us to get the actual type for both InputArg and OutputArg. rdar://9932559 llvm-svn: 167265
* This patch is to fix radar://8426430. It is about llvm support of ↵Shuxin Yang2012-10-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | | __builtin_debugtrap() which is supposed to consistently raise SIGTRAP across all systems. In contrast, __builtin_trap() behave differently on different systems. e.g. it raises SIGTRAP on ARM, and SIGILL on X86. The purpose of __builtin_debugtrap() is to consistently provide "trap" functionality, in the mean time preserve the compatibility with on gcc on __builtin_trap(). The X86 backend is already able to handle debugtrap(). This patch is to: 1) make front-end recognize "__builtin_debugtrap()" (emboddied in the one-line change to Clang). 2) In DAG legalization phase, by default, "debugtrap" will be replaced with "trap", which make the __builtin_debugtrap() "available" to all existing ports without the hassle of changing their code. 3) If trap-function is specified (via -trap-func=xyz to llc), both __builtin_debugtrap() and __builtin_trap() will be expanded into the function call of the specified trap function. This behavior may need change in the future. The provided testing-case is to make sure 2) and 3) are working for ARM port, and we already have a testing case for x86. llvm-svn: 166300
* Add in the first step of the multiple pointer support. This adds in support ↵Micah Villmow2012-10-091-6/+7
| | | | | | | | to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. llvm-svn: 165505
* Create enums for the different attributes.Bill Wendling2012-10-091-5/+5
| | | | | | | We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. llvm-svn: 165488
* Move TargetData to DataLayout.Micah Villmow2012-10-081-2/+2
| | | | llvm-svn: 165402
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-271-4/+4
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-271-4/+4
| | | | llvm-svn: 164767
* TargetLowering interface to set/get minimum block entries for jump tables.Sebastian Pop2012-09-251-0/+1
| | | | | | | | | | | | | | Provide interface in TargetLowering to set or get the minimum number of basic blocks whereby jump tables are generated for switch statements rather than an if sequence. getMinimumJumpTableEntries() defaults to 4. setMinimumJumpTableEntries() allows target configuration. This patch changes the default for the Hexagon architecture to 5 as it improves performance on some benchmarks. llvm-svn: 164628
* Add predicates for queries on whether an attribute exists.Bill Wendling2012-09-191-7/+6
| | | | llvm-svn: 164264
* Fix a few old-GCC warnings. No functional change.Nadav Rotem2012-09-061-1/+1
| | | | llvm-svn: 163309
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-051-1/+1
| | | | llvm-svn: 163258
* Generic Bypass Slow DivPreston Gurd2012-09-041-1/+0
| | | | | | | | | | | | | | | | | | | | | | | - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! llvm-svn: 163150
* TargetLowering: Use the large shift amount during legalize types. The ↵Benjamin Kramer2012-08-171-3/+3
| | | | | | legalizer may call us with an overly large type. llvm-svn: 162101
* Conform to LLVM coding style.Micah Villmow2012-07-311-2/+2
| | | | llvm-svn: 161061
* Don't generate ordered or unordered comparison operations if it is not legal ↵Micah Villmow2012-07-311-1/+2
| | | | | | to do so. llvm-svn: 161053
* Remove tabs.Bill Wendling2012-07-191-4/+6
| | | | llvm-svn: 160475
* Implement r160312 as target indepedenet dag combine.Evan Cheng2012-07-171-0/+27
| | | | llvm-svn: 160354
* Make sure constant bitwidth is <= 64 bit before calling getSExtValue().Evan Cheng2012-07-171-1/+2
| | | | llvm-svn: 160350
* This is another case where instcombine demanded bits optimization createdEvan Cheng2012-07-171-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 llvm-svn: 160346
* All cases are covered, no need for a default. This deals with theDuncan Sands2012-07-051-1/+0
| | | | | | corresponding clang warning. llvm-svn: 159742
* Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1Duncan Sands2012-07-051-9/+17
| | | | | | booleans. Patch by James Benton. llvm-svn: 159739
* Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng2012-07-021-0/+1
| | | | | | instead. llvm-svn: 159611
* Remove the "-promote-elements" flag. This flag is now enabled by default.Nadav Rotem2012-06-041-12/+1
| | | | llvm-svn: 157925
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-1/+1
| | | | llvm-svn: 157885
* Simplify code for calling a function where CanLowerReturn fails, fixing a ↵Eli Friedman2012-05-251-9/+1
| | | | | | small bug in the process. llvm-svn: 157446
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-051-0/+1
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
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