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path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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* Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. ↵Eli Friedman2012-01-311-7/+9
| | | | | | Not committing a testcase because I think it will be too fragile. llvm-svn: 149315
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-161-2/+0
| | | | | | unused variables). llvm-svn: 148230
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-5/+22
| | | | | | | | | | | We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-101-0/+1
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-1/+0
| | | | llvm-svn: 147855
* Add basic generic CodeGen support for half.Dan Gohman2011-12-201-10/+21
| | | | llvm-svn: 146927
* Don't try to form FGETSIGN after legalization; it is possible in some cases, ↵Eli Friedman2011-12-151-1/+2
| | | | | | but the existing code can't do it correctly. PR11570. llvm-svn: 146630
* Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.Eli Friedman2011-12-091-4/+3
| | | | llvm-svn: 146219
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-081-10/+20
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* Add check so we don't try to perform an impossible transformation. Fixes ↵Eli Friedman2011-11-091-1/+2
| | | | | | issue from PR11319. llvm-svn: 144216
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-1/+1
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV()Richard Osborne2011-11-071-8/+14
| | | | | | and TargetLowering::BuildUDIV(). Fixes PR11283 llvm-svn: 143964
* Change the default scheduler from Latency to ILP, since LatencyDan Gohman2011-10-241-1/+1
| | | | | | is going away. llvm-svn: 142810
* Enable element promotion type legalization by deafault.Nadav Rotem2011-10-161-1/+1
| | | | | | Changed tests which assumed that vectors are legalized by widening them. llvm-svn: 142152
* Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4".Jim Grosbach2011-10-141-1/+1
| | | | | | Pointed out by George Russell. llvm-svn: 141956
* Use an existing function.Jakob Stoklund Olesen2011-10-121-10/+2
| | | | llvm-svn: 141763
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-2/+4
| | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
* Fix a truly heinous bug in DAGCombine related to AssertZext.Owen Anderson2011-09-031-7/+6
| | | | | | | If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem. Fixes <rdar://problem/10063365>. llvm-svn: 139059
* New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman2011-08-031-0/+1
| | | | | | | | platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. llvm-svn: 136813
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-7/+7
| | | | llvm-svn: 135375
* Check register class matching instead of width of type matchingEric Christopher2011-07-141-2/+5
| | | | | | | | | when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-081-0/+4
| | | | | | is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
* Emit a more efficient magic number multiplication for exact sdivs.Benjamin Kramer2011-07-081-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building. struct foo { char x[24]; }; long bar(struct foo *a, struct foo *b) { return a-b; } is now compiled into movl 4(%esp), %eax subl 8(%esp), %eax sarl $3, %eax imull $-1431655765, %eax, %eax instead of movl 4(%esp), %eax subl 8(%esp), %eax movl $715827883, %ecx imull %ecx movl %edx, %eax shrl $31, %eax sarl $2, %edx addl %eax, %edx movl %edx, %eax llvm-svn: 134695
* Remove a FIXME. All of the standard ones are in the list.Eric Christopher2011-07-071-1/+0
| | | | llvm-svn: 134647
* Remove getRegClassForInlineAsmConstraint and all dependencies.Eric Christopher2011-06-301-7/+0
| | | | | | Fixes rdar://9643582 llvm-svn: 134123
* Lower multiply with overflow checking to __mulo<mode>Eric Christopher2011-06-171-4/+7
| | | | | | | | | calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
* Fix a bug in the calculation of the vectorTypeBreakdown into registers. OddNadav Rotem2011-06-121-5/+17
| | | | | | types such as i33 were rounded to i32. Originated from Duncan's testcase. llvm-svn: 132893
* Revert r132871.Chad Rosier2011-06-111-1/+1
| | | | llvm-svn: 132872
* Typo.Chad Rosier2011-06-111-1/+1
| | | | llvm-svn: 132871
* Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings2011-06-061-6/+8
| | | | llvm-svn: 132681
* TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem2011-06-041-16/+22
| | | | | | | | | (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-021-2/+6
| | | | | | Part of rdar://9119939 llvm-svn: 132510
* Revert 132424 to fix PR10068.Rafael Espindola2011-06-021-5/+4
| | | | llvm-svn: 132479
* Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings2011-06-011-4/+5
| | | | llvm-svn: 132424
* Fix double FGETSIGN to work on x86_32; followup to 132396.Stuart Hastings2011-06-011-3/+6
| | | | | | rdar://problem/5660695 llvm-svn: 132411
* Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695Stuart Hastings2011-06-011-6/+2
| | | | llvm-svn: 132396
* This patch is another step in the direction of adding vector select. In thisNadav Rotem2011-06-011-1/+28
| | | | | | | | | patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. llvm-svn: 132394
* Refactor the type legalizer. Switch TargetLowering to a new enum - ↵Nadav Rotem2011-05-281-10/+12
| | | | | | | | | | | LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
* Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem2011-05-271-1/+1
| | | | | | code in one place. Re-apply 131534 and fix the multi-step promotion of integers. llvm-svn: 132217
* Update some currently-disabled code, preparing for eventual use.Stuart Hastings2011-05-191-6/+7
| | | | llvm-svn: 131663
* Revert commit 131534 since it seems to have broken several buildbots.Duncan Sands2011-05-181-1/+1
| | | | | | | | Original log entry: Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' code in one place. llvm-svn: 131536
* Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem2011-05-181-1/+1
| | | | | | code in one place. llvm-svn: 131534
* Look through struct wrapped types for inline asm statments.Eric Christopher2011-05-091-0/+6
| | | | | | Patch by Evan Cheng. llvm-svn: 131093
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-061-0/+2
| | | | | | functionality change. llvm-svn: 131012
* DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.Benjamin Kramer2011-04-221-0/+36
| | | | | | | | | | | | On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) llvm-svn: 130005
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-5/+4
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* sink a call into its only use.Chris Lattner2011-04-141-2/+1
| | | | llvm-svn: 129503
* During post-legalization DAG combining, be careful to only create shifts ↵Owen Anderson2011-04-131-1/+8
| | | | | | where the RHS is of the legal type for the new operation. llvm-svn: 129484
* Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng2011-04-011-0/+13
| | | | | | rdar://8911343 llvm-svn: 128696
* BuildUDIV: If the divisor is even we can simplify the fixup of the ↵Benjamin Kramer2011-03-171-9/+22
| | | | | | | | | | | | | | | | | | | | | | | multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
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