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path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-2/+0
| | | | llvm-svn: 148578
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-181-0/+1
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
* Allow targets to select source order pre-RA scheduler.Evan Cheng2012-01-121-1/+2
| | | | llvm-svn: 148033
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Allow inlining of functions with returns_twice calls, if they have theJoerg Sonnenberger2011-12-181-1/+1
| | | | | | attribute themselve. llvm-svn: 146851
* Update DebugLoc while merging nodes at -O0.Devang Patel2011-12-151-1/+1
| | | | | | Patch by Kyriakos Georgiou! llvm-svn: 146670
* [fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2.Chad Rosier2011-12-131-1/+6
| | | | llvm-svn: 146453
* Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson2011-12-081-1/+5
| | | | | | can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. llvm-svn: 146193
* Add rather verbose stats for fast-isel failures.Chad Rosier2011-12-081-0/+153
| | | | llvm-svn: 146186
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+2
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-3/+3
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Fix the stats collection for fast-isel. The failed count was only accountingChad Rosier2011-11-161-5/+18
| | | | | | | | | for a single miss and not all predecessor instructions that get selected by the selection DAG instruction selector. This is still not exact (e.g., over states misses when folded/dead instructions are present), but it is a step in the right direction. llvm-svn: 144832
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-151-2/+2
| | | | llvm-svn: 144648
* Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman2011-11-121-4/+4
| | | | | | runs. Fixes PR11029. llvm-svn: 144438
* Delete the Latency scheduling preference.Dan Gohman2011-10-241-2/+0
| | | | llvm-svn: 142815
* Correct over-zealous removal of hack.Bill Wendling2011-10-171-1/+1
| | | | | | | Some code want to check that *any* call within a function has the 'returns twice' attribute, not just that the current function has one. llvm-svn: 142221
* Now that we have the ReturnsTwice function attribute, this method isBill Wendling2011-10-171-1/+1
| | | | | | | obsolete. Check the attribute instead. <rdar://problem/8031714> llvm-svn: 142212
* Modify the mapping from landing pad to call sites to accept more than one callBill Wendling2011-10-051-0/+3
| | | | | | site. llvm-svn: 141226
* Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling2011-10-051-7/+7
| | | | llvm-svn: 141221
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-211-6/+3
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-1/+6
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-6/+1
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* whitespaceAndrew Trick2011-09-201-4/+4
| | | | llvm-svn: 140133
* Follow up to r138791.Evan Cheng2011-08-301-0/+10
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* A landingpad instruction is neither folded nor dead.Bill Wendling2011-08-231-0/+1
| | | | llvm-svn: 138387
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-0/+1
| | | | | | when building with assertions disabled. llvm-svn: 137460
* fix PR10605 / rdar://9930964 by adding a pretty scary missed check.Chris Lattner2011-08-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | It's somewhat surprising anything works without this. Before we would compile the testcase into: test: # @test movl $4, 8(%rdi) movl 8(%rdi), %eax orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 now we produce: test: # @test movl 8(%rdi), %eax movl $4, 8(%rdi) orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 llvm-svn: 137303
* Revert r135423.Devang Patel2011-07-191-2/+0
| | | | llvm-svn: 135454
* During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel2011-07-181-0/+2
| | | | | | | | at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. [take 2] llvm-svn: 135423
* Revert r133953 for now.Devang Patel2011-06-291-2/+0
| | | | llvm-svn: 134116
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-6/+6
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel2011-06-271-0/+2
| | | | | | at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. llvm-svn: 133953
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-161-0/+15
| | | | | | | | BranchProbabilityInfo (expect setEdgeWeight which is not available here). Branch Weights are kept in MachineBasicBlocks. To turn off this analysis set -use-mbpi=false. llvm-svn: 133184
* Remove unused statistical counter.Devang Patel2011-05-251-57/+0
| | | | llvm-svn: 132087
* Preserve debug info during iSel by keeping DanglingDebugInfoMap live until ↵Devang Patel2011-05-231-0/+1
| | | | | | | | end of function. Patch by Micah Villmow llvm-svn: 131908
* Fix PR9955 by only attaching load memory operands to load instructions andCameron Zwarich2011-05-191-3/+37
| | | | | | | similarly for stores. Now "make check" passes with the MachineVerifier forced on with the VerifyCoalescing option! llvm-svn: 131705
* Make fast-isel miss counting in -stats and -fast-isel-verbose take ↵Eli Friedman2011-05-171-3/+8
| | | | | | terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant. llvm-svn: 131502
* Delete unused variables.Dan Gohman2011-05-161-1/+1
| | | | llvm-svn: 131430
* Track how many insns fast-isel successfully selects as well as how many itJim Grosbach2011-05-161-0/+2
| | | | | | misses. llvm-svn: 131426
* Don't do tail calls in a function that call setjmp. The stack might beRafael Espindola2011-05-161-33/+1
| | | | | | corrupted when setjmp returns again. llvm-svn: 131399
* Use array_lengthof. No functional change.Eli Friedman2011-05-061-3/+1
| | | | llvm-svn: 131008
* Small syntax cleanup; we don't need to #define constants in C++. No ↵Eli Friedman2011-05-051-3/+3
| | | | | | functionality change intended. llvm-svn: 130926
* Recommit the fix for rdar://9289512 with a couple tweaks toChris Lattner2011-04-221-17/+54
| | | | | | | | | | | fix bugs exposed by the gcc dejagnu testsuite: 1. The load may actually be used by a dead instruction, which would cause an assert. 2. The load may not be used by the current chain of instructions, and we could move it past a side-effecting instruction. Change how we process uses to define the problem away. llvm-svn: 130018
* Revert r1296656, "Fix rdar://9289512 - not folding load into compare at -O0...",Daniel Dunbar2011-04-211-41/+15
| | | | | | which broke a couple GCC test suite tests at -O0. llvm-svn: 129914
* SelectBasicBlock is rather slow even when it doesn't do anything; skip theEli Friedman2011-04-191-5/+7
| | | | | | unnecessary work where possible. llvm-svn: 129763
* fix an oversight which caused us to compile the testcase (and otherChris Lattner2011-04-171-5/+3
| | | | | | | | | | | | | | | | | | | less trivial things) into a dummy lea. Before we generated: _test: ## @test movq _G@GOTPCREL(%rip), %rax leaq (%rax), %rax ret now we produce: _test: ## @test movq _G@GOTPCREL(%rip), %rax ret This is part of rdar://9289558 llvm-svn: 129662
* Fix rdar://9289512 - not folding load into compare at -O0Chris Lattner2011-04-171-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | The basic issue here is that bottom-up isel is matching the branch and compare, and was failing to fold the load into the branch/compare combo. Fixing this (by allowing folding into any instruction of a sequence that is selected) allows us to produce things like: cmpb $0, 52(%rax) je LBB4_2 instead of: movb 52(%rax), %cl cmpb $0, %cl je LBB4_2 This makes the generated -O0 code run a bit faster, but also speeds up compile time by putting less pressure on the register allocator and generating less code. This was one of the biggest classes of missing load folding. Implementing this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm) line count. llvm-svn: 129656
* split a complex predicate out to a helper function. Simplify two for loops,Chris Lattner2011-04-171-10/+16
| | | | | | | which don't need to check for falling off the end of a block *and* end of phi nodes, since terminators are never phis. llvm-svn: 129655
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