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path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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* remove the read/write port/io intrinsics.Chris Lattner2006-03-031-23/+0
| | | | llvm-svn: 26479
* Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolvingChris Lattner2006-03-031-3/+12
| | | | | | PR709, and paving the way for future progress. llvm-svn: 26476
* Vector ops lowering.Evan Cheng2006-03-011-4/+10
| | | | llvm-svn: 26436
* Add support for output memory constraints.Chris Lattner2006-02-271-7/+38
| | | | llvm-svn: 26410
* Get VC++ building again.Jeff Cohen2006-02-241-0/+1
| | | | llvm-svn: 26351
* Implement (most of) selection of inline asm memory operands.Chris Lattner2006-02-241-0/+42
| | | | llvm-svn: 26350
* Lower C_Memory operands.Chris Lattner2006-02-241-25/+44
| | | | llvm-svn: 26346
* Fix an endianness problem on big-endian targets with expanded operandsChris Lattner2006-02-231-9/+16
| | | | | | to inline asms. Mark some methods const. llvm-svn: 26334
* Record all of the expanded registers in the DAG and machine instr, fixingChris Lattner2006-02-231-63/+105
| | | | | | several bugs in inline asm expanded operands. llvm-svn: 26332
* This fixes a couple of problems with expansionChris Lattner2006-02-221-9/+23
| | | | llvm-svn: 26318
* Change a whole bunch of code to be built around RegsForValue instead ofChris Lattner2006-02-221-124/+248
| | | | | | | a single register number. This fully implements promotion for inline asms, expand is close but not quite right yet. llvm-svn: 26316
* split register class handling from explicit physreg handling.Chris Lattner2006-02-221-34/+77
| | | | llvm-svn: 26308
* Adjust to changes in getRegForInlineAsmConstraint prototypeChris Lattner2006-02-211-18/+18
| | | | llvm-svn: 26306
* Dumb bug. Code sees a memcpy from X+c so it increments src offset. But itEvan Cheng2006-02-161-4/+10
| | | | | | | turns out not to point to a constant string but it forgot change the offset back. llvm-svn: 26242
* If the false case is the current basic block, then this is a self loop.Evan Cheng2006-02-161-0/+9
| | | | | | | | | | We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. llvm-svn: 26231
* Remove an unused function parameter.Evan Cheng2006-02-151-2/+2
| | | | llvm-svn: 26221
* Turn a memcpy from string constant into a series of stores of constant values.Evan Cheng2006-02-151-47/+69
| | | | llvm-svn: 26219
* Lower memcpy with small constant size operand into a series of load / storeEvan Cheng2006-02-151-8/+34
| | | | | | ops. llvm-svn: 26195
* Doh again!Evan Cheng2006-02-141-1/+1
| | | | llvm-svn: 26188
* Keep to < 80 colsEvan Cheng2006-02-141-6/+6
| | | | llvm-svn: 26177
* Missed a break so memcpy cases fell through to memset. Doh.Evan Cheng2006-02-141-1/+1
| | | | llvm-svn: 26176
* Fixed a build breakage.Evan Cheng2006-02-141-14/+23
| | | | llvm-svn: 26175
* Rename maxStoresPerMemSet to maxStoresPerMemset, etc.Evan Cheng2006-02-141-1/+1
| | | | llvm-svn: 26174
* Expand memset dst, c, size to a series of stores if size falls below theEvan Cheng2006-02-141-4/+127
| | | | | | target specific theshold, e.g. 16 for x86. llvm-svn: 26171
* now that libcalls don't suck, we can remove this hackChris Lattner2006-02-141-6/+2
| | | | llvm-svn: 26164
* Rename to better reflect usage (current and planned.)Jim Laskey2006-02-131-1/+1
| | | | llvm-svn: 26145
* Reorg for integration with gcc4. Old style debug info will not be passed thoughJim Laskey2006-02-111-24/+21
| | | | | | to SelIDAG. llvm-svn: 26115
* Get rid of some memory leaks identified by ValgrindEvan Cheng2006-02-041-0/+1
| | | | llvm-svn: 25960
* Add initial support for immediates. This allows us to compile this:Chris Lattner2006-02-041-1/+1
| | | | | | | | | | | | | | | | | | int %rlwnm(int %A, int %B) { %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17) ret int %C } into: _rlwnm: or r2, r3, r3 or r3, r4, r4 rlwnm r2, r2, r3, 4, 17 ;; note the immediates :) or r3, r2, r2 blr llvm-svn: 25955
* Initial early support for non-register operands, like immediatesChris Lattner2006-02-041-15/+42
| | | | llvm-svn: 25952
* remove some #ifdef'd out code, which should properly be in the dag combiner ↵Chris Lattner2006-02-031-30/+0
| | | | | | anyway. llvm-svn: 25941
* Implement matching constraints. We can now say things like this:Chris Lattner2006-02-021-15/+28
| | | | | | | | | | | | | | %C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4) and get: xyz r2, r3, r4, r2 note that the r2's are pinned together. Yaay for 2-address instructions. 2342 ---------------------------------------------------------------------- llvm-svn: 25893
* Implement simple register assignment for inline asms. This allows us to ↵Chris Lattner2006-02-011-8/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | compile: int %test(int %A, int %B) { %C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B) ret int %C } into: (0x8906130, LLVM BB @0x8902220): %r2 = OR4 %r3, %r3 %r3 = OR4 %r4, %r4 INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3 %r3 = OR4 %r2, %r2 BLR which asmprints as: _test: or r2, r3, r3 or r3, r4, r4 xyz $0, $1, $2 ;; need to print the operands now :) or r3, r2, r2 blr llvm-svn: 25878
* adjust to changes in InlineAsm interface. Fix a few minor bugs.Chris Lattner2006-02-011-32/+38
| | | | llvm-svn: 25865
* Handle physreg input/outputs. We now compile this:Chris Lattner2006-01-311-3/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int %test_cpuid(int %op) { %B = alloca int %C = alloca int %D = alloca int %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op) %Bv = load int* %B %Cv = load int* %C %Dv = load int* %D %x = add int %A, %Bv %y = add int %x, %Cv %z = add int %y, %Dv ret int %z } to this: _test_cpuid: sub %ESP, 16 mov DWORD PTR [%ESP], %EBX mov %EAX, DWORD PTR [%ESP + 20] cpuid mov DWORD PTR [%ESP + 8], %ECX mov DWORD PTR [%ESP + 12], %EBX mov DWORD PTR [%ESP + 4], %EDX mov %ECX, DWORD PTR [%ESP + 12] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 8] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 4] add %EAX, %ECX mov %EBX, DWORD PTR [%ESP] add %ESP, 16 ret ... note the proper register allocation. :) it is unclear to me why the loads aren't folded into the adds. llvm-svn: 25827
* remove method I just addedChris Lattner2006-01-281-7/+0
| | | | llvm-svn: 25728
* add a new callbackChris Lattner2006-01-281-0/+7
| | | | llvm-svn: 25727
* Implement Promote for VAARG, and allow it to be custom promoted for peopleNate Begeman2006-01-281-0/+7
| | | | | | who don't want the default behavior (Alpha). llvm-svn: 25726
* Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET forNate Begeman2006-01-271-37/+22
| | | | | | | the same functionality. This addresses another piece of bug 680. Next, on to fixing Alpha VAARG, which I broke last time. llvm-svn: 25696
* initial selectiondag support for new INLINEASM node. Note that inline asmsChris Lattner2006-01-261-0/+50
| | | | | | with outputs or inputs are not supported yet. :) llvm-svn: 25664
* First part of bug 680:Nate Begeman2006-01-251-53/+16
| | | | | | | Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else. llvm-svn: 25606
* If scheduler choice is the default (-sched=default), use target schedulingEvan Cheng2006-01-251-2/+10
| | | | | | | | preference to determine which scheduler to use. SchedulingForLatency == Breadth first; SchedulingForRegPressure == bottom up register reduction list scheduler. llvm-svn: 25599
* Typo.Jim Laskey2006-01-231-1/+1
| | | | llvm-svn: 25545
* Skeleton of the list schedule.Evan Cheng2006-01-231-0/+4
| | | | llvm-svn: 25544
* Factor out more instruction scheduler code to the base class.Evan Cheng2006-01-231-1/+29
| | | | llvm-svn: 25532
* Fix bugs lowering stackrestore, fixing 2004-08-12-InlinerAndAllocas.c onChris Lattner2006-01-231-3/+4
| | | | | | PPC. llvm-svn: 25522
* Fix a bug in a recent refactor that caused a bunch of programs to miscompileChris Lattner2006-01-211-1/+1
| | | | | | or the compiler to crash. llvm-svn: 25503
* Do some code refactoring on Jim's scheduler in preparation of the new listEvan Cheng2006-01-211-4/+18
| | | | | | scheduler. llvm-svn: 25493
* If the target doesn't support f32 natively, insert the FP_EXTEND in target-indepChris Lattner2006-01-201-0/+4
| | | | | | code, so that the LowerReturn code doesn't have to handle it. llvm-svn: 25482
* Temporary work around for a libcall insertion bug: If a target doesn'tChris Lattner2006-01-181-2/+6
| | | | | | support FSIN/FCOS nodes, do not lower sin/cos to them. llvm-svn: 25425
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