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path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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* Reapply an improved version of r180816/180817.Adrian Prantl2013-07-091-7/+9
| | | | | | | | | | | | | | | Change the informal convention of DBG_VALUE machine instructions so that we can express a register-indirect address with an offset of 0. The old convention was that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain register values the combination reg, reg is used. MachineInstrBuilder::BuildMI knows how to build the new DBG_VALUES. rdar://problem/13658587 llvm-svn: 185966
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-041-4/+7
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185617
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-7/+4
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-031-4/+7
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185595
* Use SmallVectorImpl::const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-031-4/+4
| | | | | | specifying the vector size. llvm-svn: 185514
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-11/+14
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-161-1/+4
| | | | | | | | | | | | | | | | | | | | Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. llvm-svn: 184066
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-18/+17
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Don't cache the TargetLoweringInfo object inside of the FunctionLowering object.Bill Wendling2013-06-061-1/+1
| | | | | | | | The TargetLoweringInfo object is owned by the TargetMachine. In the future, the TargetMachine object may change, which may also change the TargetLoweringInfo object. llvm-svn: 183356
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-251-3/+1
| | | | | | | Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. llvm-svn: 182704
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-4/+4
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Temporarily revert "Change the informal convention of DBG_VALUE so that we ↵Adrian Prantl2013-04-301-10/+7
| | | | | | | | | | can express a" because it breaks some buildbots. This reverts commit 180816. llvm-svn: 180819
* Change the informal convention of DBG_VALUE so that we can express aAdrian Prantl2013-04-301-7/+10
| | | | | | | | | | | | register-indirect address with an offset of 0. It used to be that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain registers use the combination reg, reg. rdar://problem/13658587 llvm-svn: 180816
* Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'mEli Bendersky2013-04-191-79/+1
| | | | | | | trying to move as much FastISel logic as possible out of the main path in SelectionDAGISel - intermixing them just adds confusion. llvm-svn: 179902
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-191-1/+1
| | | | llvm-svn: 179901
* Use dbgs() consistently for -debug printoutsEli Bendersky2013-04-191-13/+13
| | | | llvm-svn: 179894
* Add some more stats for fast isel vs. SelectionDAG, w.r.t lowering functionEli Bendersky2013-04-191-1/+10
| | | | | | arguments in entry BBs. llvm-svn: 179824
* Move SDNode order propagation to SDNodeOrdering, which also fixes a missedJustin Holewinski2013-03-201-0/+2
| | | | | | | | case of order propagation during isel. Thanks Owen for the suggestion! llvm-svn: 177525
* Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski2013-03-201-1/+3
| | | | | | | | A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. llvm-svn: 177465
* Reset some of the target options which affect code generation.Bill Wendling2013-03-131-0/+1
| | | | | | | | This doesn't reset all of the target options within the TargetOptions object. This is because some of those are ABI-specific and must be determined if it's okay to change those on the fly. llvm-svn: 176986
* Disable statistics on Release builds and move tests that depend on -stats.Jan Wen Voung2013-03-081-13/+11
| | | | | | | | | | | | | | | | | Summary: Statistics are still available in Release+Asserts (any +Asserts builds), and stats can also be turned on with LLVM_ENABLE_STATS. Move some of the FastISel stats that were moved under DEBUG() back out of DEBUG(), since stats are disabled across the board now. Many tests depend on grepping "-stats" output. Move those into a orig_dir/Stats/. so that they can be marked as unsupported when building without statistics. Differential Revision: http://llvm-reviews.chandlerc.com/D486 llvm-svn: 176733
* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-071-3/+1
| | | | llvm-svn: 176648
* No need to go through int64 and APInt when generating a new constant.Nadav Rotem2013-03-071-3/+3
| | | | llvm-svn: 176615
* Remove duplicate line and move another closer to its actual useEli Bendersky2013-03-011-3/+1
| | | | llvm-svn: 176391
* A small refactoring + adding comments.Eli Bendersky2013-02-281-7/+4
| | | | | | | | | | | SelectionDAGIsel::LowerArguments needs a function, not a basic block. So it makes sense to pass it the function instead of extracting a basic-block from the function and then tossing it. This is also more self-documenting (functions have arguments, BBs don't). In addition, added comments to a couple of Select* methods. llvm-svn: 176305
* Remove unnecessary cast to void.Eric Christopher2013-02-271-1/+0
| | | | llvm-svn: 176222
* Silence the unused variable warning. Nadav Rotem2013-02-271-5/+7
| | | | llvm-svn: 176218
* The FastISEL should be fast. But when we record statistics we use atomic ↵Nadav Rotem2013-02-271-9/+10
| | | | | | | | operations to increment the counters. This patch disables the counters on non-debug builds. This reduces the runtime of SelectionDAGISel::SelectCodeCommon by ~5%. llvm-svn: 176214
* Fix wording.Chad Rosier2013-02-251-3/+4
| | | | llvm-svn: 176055
* [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 orChad Rosier2013-02-251-0/+10
| | | | | | | | | | fewer scalar integer (i32 or i64) arguments. It completely eliminates the need for SDISel for trivial functions. Also, add the new llc -fast-isel-abort-args option, which is similar to -fast-isel-abort option, but for formal argument lowering. llvm-svn: 176052
* [ms-inline asm] Remove a redundant call to the setHasMSInlineAsm function.Chad Rosier2013-02-181-2/+1
| | | | llvm-svn: 175456
* [ms-inline asm] Fix undefined behavior to reset hasMSInlineAsm in advance of ↵NAKAMURA Takumi2013-02-181-0/+1
| | | | | | SelectAllBasicBlocks(). llvm-svn: 175422
* [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.Chad Rosier2013-02-161-14/+17
| | | | | | | | | | | If the frame pointer is omitted, and any stack changes occur in the inline assembly, e.g.: "pusha", then any C local variable or C argument references will be incorrect. I pass no judgement on anyone who would do such a thing. ;) rdar://13218191 llvm-svn: 175334
* Use the 'target-features' and 'target-cpu' attributes to reset the subtarget ↵Bill Wendling2013-02-151-0/+4
| | | | | | | | | | features. If two functions require different features (e.g., `-mno-sse' vs. `-msse') then we want to honor that, especially during LTO. We can do that by resetting the subtarget's features depending upon the 'target-feature' attribute. llvm-svn: 175314
* Currently, codegen may spent some time in SDISel passes even if an entireEvan Cheng2013-02-111-7/+13
| | | | | | | | | | | | | | function is successfully handled by fast-isel. That's because function arguments are *always* handled by SDISel. Introduce FastLowerArguments to allow each target to provide hook to handle formal argument lowering. As a proof-of-concept, add ARMFastIsel::FastLowerArguments to handle functions with 4 or fewer scalar integer (i8, i16, or i32) arguments. It completely eliminates the need for SDISel for trivial functions. rdar://13163905 llvm-svn: 174855
* Move TargetTransformInfo to live under the Analysis library. This noChandler Carruth2013-01-071-1/+1
| | | | | | | longer would violate any dependency layering and it is in fact an analysis. =] llvm-svn: 171686
* Funnel the actual TargetTransformInfo pass from the SelectionDAGISelChandler Carruth2013-01-051-1/+3
| | | | | | | | | pass into the SelectionDAG itself rather than snooping on the implementation of that pass as exposed by the TargetMachine. This removes the last direct client of the ScalarTargetTransformInfo class outside of the TTI pass implementation. llvm-svn: 171625
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-8/+8
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use MachineInstrBuilder for PHI nodes in SelectionDAGISel.Jakob Stoklund Olesen2012-12-201-50/+25
| | | | llvm-svn: 170716
* Fall back to the selection dag isel to select tail calls.Chad Rosier2012-12-111-5/+7
| | | | | | | | | | | | | | | | | | | This shouldn't affect codegen for -O0 compiles as tail call markers are not emitted in unoptimized compiles. Testing with the external/internal nightly test suite reveals no change in compile time performance. Testing with -O1, -O2 and -O3 with fast-isel enabled did not cause any compile-time or execution-time failures. All tests were performed on my x86 machine. I'll monitor our arm testers to ensure no regressions occur there. In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While it's theoretically true that this is just an optimization, it's an optimization that we very much want to happen even at -O0, or else ARC applications become substantially harder to debug. Part of rdar://12553082 llvm-svn: 169796
* Use dyn_cast instead of isa and cast. No functionality change.Jakub Staszak2012-12-041-4/+4
| | | | llvm-svn: 169196
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-20/+20
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* misched: Allow subtargets to enable misched and dependent options.Andrew Trick2012-11-131-1/+3
| | | | | | | | | | | | This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
* Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen2012-10-151-0/+5
| | | | | | | | | | | | | Also provide an MRI::getReservedRegs() function to access the frozen register set, and isReserved() and isAllocatable() methods to test individual registers. The various implementations of TRI::getReservedRegs() are quite complicated, and many passes need to look at the reserved register set. This patch makes it possible for these passes to use the cached copy in MRI, avoiding a lot of malloc traffic and repeated calculations. llvm-svn: 165982
* Fix bad comment. No functional change.Craig Topper2012-09-161-1/+1
| | | | llvm-svn: 164000
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-061-4/+9
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* BranchProb: modify the definition of an edge in BranchProbabilityInfo to handleManman Ren2012-08-241-0/+7
| | | | | | | | | | | | | | the case of multiple edges from one block to another. A simple example is a switch statement with multiple values to the same destination. The definition of an edge is modified from a pair of blocks to a pair of PredBlock and an index into the successors. Also set the weight correctly when building SelectionDAG from LLVM IR, especially when converting a Switch. IntegersSubsetMapping is updated to calculate the weight for each cluster. llvm-svn: 162572
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-2/+2
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Fall back to selection DAG isel for calls to builtin functions.Bob Wilson2012-08-031-1/+1
| | | | | | | | | | Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> llvm-svn: 161232
* Provide function name in 'Cannot select' fatal error.Jim Grosbach2012-07-131-0/+1
| | | | | | | | | When dumping the DAG for a fatal 'Cannot select' back-end error, also provide the name of the function the construct is in. Useful when dealing with large testcases, as the next step is to llvm-extract the function in question to get a small(er) testcase. llvm-svn: 160152
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