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* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-281-5/+5
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* Add some constantness. No functionality change.Jakub Staszak2012-04-301-9/+9
| | | | llvm-svn: 155859
* Fix PR12599.Jakob Stoklund Olesen2012-04-201-1/+6
| | | | | | | | The X86 target is editing the selection DAG while isel is selecting nodes following a topological ordering. When the DAG hacking triggers CSE, nodes can be deleted and bad things happen. llvm-svn: 155257
* Make ISelPosition a local variable.Jakob Stoklund Olesen2012-04-201-8/+25
| | | | | | | | | Now that multiple DAGUpdateListeners can be active at the same time, ISelPosition can become a local variable in DoInstructionSelection. We simply register an ISelUpdater with CurDAG while ISelPosition exists. llvm-svn: 155249
* Register DAGUpdateListeners with SelectionDAG.Jakob Stoklund Olesen2012-04-201-6/+6
| | | | | | | | | | | | | | | Instead of passing listener pointers to RAUW, let SelectionDAG itself keep a linked list of interested listeners. This makes it possible to have multiple listeners active at once, like RAUWUpdateListener was already doing. It also makes it possible to register listeners up the call stack without controlling all RAUW calls below. DAGUpdateListener uses an RAII pattern to add itself to the SelectionDAG list of active listeners. llvm-svn: 155248
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-4/+2
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-3/+4
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* whitespaceAndrew Trick2012-03-071-3/+3
| | | | llvm-svn: 152175
* Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames2012-02-141-1/+1
| | | | | | consistency with setExceptionPointerRegister(...). llvm-svn: 150460
* [unwind removal] Remove all of the code for the dead 'unwind' instruction. ThereBill Wendling2012-02-061-2/+0
| | | | | | | were no 'unwind' instructions being generated before this, so this is in effect a no-op. llvm-svn: 149906
* VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick2012-02-011-0/+2
| | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
* Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copyBill Wendling2012-01-311-25/+0
| | | | | | | over the catch information. The catch information is now tacked to the invoke instruction. llvm-svn: 149326
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-2/+0
| | | | llvm-svn: 148578
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-181-0/+1
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
* Allow targets to select source order pre-RA scheduler.Evan Cheng2012-01-121-1/+2
| | | | llvm-svn: 148033
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Allow inlining of functions with returns_twice calls, if they have theJoerg Sonnenberger2011-12-181-1/+1
| | | | | | attribute themselve. llvm-svn: 146851
* Update DebugLoc while merging nodes at -O0.Devang Patel2011-12-151-1/+1
| | | | | | Patch by Kyriakos Georgiou! llvm-svn: 146670
* [fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2.Chad Rosier2011-12-131-1/+6
| | | | llvm-svn: 146453
* Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson2011-12-081-1/+5
| | | | | | can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. llvm-svn: 146193
* Add rather verbose stats for fast-isel failures.Chad Rosier2011-12-081-0/+153
| | | | llvm-svn: 146186
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+2
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-3/+3
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Fix the stats collection for fast-isel. The failed count was only accountingChad Rosier2011-11-161-5/+18
| | | | | | | | | for a single miss and not all predecessor instructions that get selected by the selection DAG instruction selector. This is still not exact (e.g., over states misses when folded/dead instructions are present), but it is a step in the right direction. llvm-svn: 144832
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-151-2/+2
| | | | llvm-svn: 144648
* Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman2011-11-121-4/+4
| | | | | | runs. Fixes PR11029. llvm-svn: 144438
* Delete the Latency scheduling preference.Dan Gohman2011-10-241-2/+0
| | | | llvm-svn: 142815
* Correct over-zealous removal of hack.Bill Wendling2011-10-171-1/+1
| | | | | | | Some code want to check that *any* call within a function has the 'returns twice' attribute, not just that the current function has one. llvm-svn: 142221
* Now that we have the ReturnsTwice function attribute, this method isBill Wendling2011-10-171-1/+1
| | | | | | | obsolete. Check the attribute instead. <rdar://problem/8031714> llvm-svn: 142212
* Modify the mapping from landing pad to call sites to accept more than one callBill Wendling2011-10-051-0/+3
| | | | | | site. llvm-svn: 141226
* Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling2011-10-051-7/+7
| | | | llvm-svn: 141221
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-211-6/+3
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-1/+6
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-6/+1
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* whitespaceAndrew Trick2011-09-201-4/+4
| | | | llvm-svn: 140133
* Follow up to r138791.Evan Cheng2011-08-301-0/+10
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* A landingpad instruction is neither folded nor dead.Bill Wendling2011-08-231-0/+1
| | | | llvm-svn: 138387
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-0/+1
| | | | | | when building with assertions disabled. llvm-svn: 137460
* fix PR10605 / rdar://9930964 by adding a pretty scary missed check.Chris Lattner2011-08-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | It's somewhat surprising anything works without this. Before we would compile the testcase into: test: # @test movl $4, 8(%rdi) movl 8(%rdi), %eax orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 now we produce: test: # @test movl 8(%rdi), %eax movl $4, 8(%rdi) orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 llvm-svn: 137303
* Revert r135423.Devang Patel2011-07-191-2/+0
| | | | llvm-svn: 135454
* During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel2011-07-181-0/+2
| | | | | | | | at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. [take 2] llvm-svn: 135423
* Revert r133953 for now.Devang Patel2011-06-291-2/+0
| | | | llvm-svn: 134116
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-6/+6
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel2011-06-271-0/+2
| | | | | | at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. llvm-svn: 133953
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-161-0/+15
| | | | | | | | BranchProbabilityInfo (expect setEdgeWeight which is not available here). Branch Weights are kept in MachineBasicBlocks. To turn off this analysis set -use-mbpi=false. llvm-svn: 133184
* Remove unused statistical counter.Devang Patel2011-05-251-57/+0
| | | | llvm-svn: 132087
* Preserve debug info during iSel by keeping DanglingDebugInfoMap live until ↵Devang Patel2011-05-231-0/+1
| | | | | | | | end of function. Patch by Micah Villmow llvm-svn: 131908
* Fix PR9955 by only attaching load memory operands to load instructions andCameron Zwarich2011-05-191-3/+37
| | | | | | | similarly for stores. Now "make check" passes with the MachineVerifier forced on with the VerifyCoalescing option! llvm-svn: 131705
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