summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* correct this logic.Chris Lattner2010-09-211-2/+2
| | | | llvm-svn: 114474
* just like they can opt into getting the root of the pattern beingChris Lattner2010-09-211-1/+5
| | | | | | | matched, allow ComplexPatterns to opt into getting the parent node of the operand being matched. llvm-svn: 114472
* implement rdar://6653118 - fastisel should fold loads where possible.Chris Lattner2010-09-051-1/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since mem2reg isn't run at -O0, we get a ton of reloads from the stack, for example, before, this code: int foo(int x, int y, int z) { return x+y+z; } used to compile into: _foo: ## @foo subq $12, %rsp movl %edi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movl 8(%rsp), %edx movl 4(%rsp), %esi addl %edx, %esi movl (%rsp), %edx addl %esi, %edx movl %edx, %eax addq $12, %rsp ret Now we produce: _foo: ## @foo subq $12, %rsp movl %edi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movl 8(%rsp), %edx addl 4(%rsp), %edx ## Folded load addl (%rsp), %edx ## Folded load movl %edx, %eax addq $12, %rsp ret Fewer instructions and less register use = faster compiles. llvm-svn: 113102
* zap dead code.Chris Lattner2010-08-261-32/+0
| | | | llvm-svn: 112155
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng2010-07-241-2/+4
| | | | | | | | | | | | appropriate for targets without detailed instruction iterineries. The scheduler schedules for increased instruction level parallelism in low register pressure situation; it schedules to reduce register pressure when the register pressure becomes high. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%. llvm-svn: 109300
* mass elimination of reliance on automatic iterator dereferencingGabor Greif2010-07-221-1/+1
| | | | llvm-svn: 109103
* Use the source-order scheduler instead of the "fast" scheduler at -O0,Dan Gohman2010-07-161-1/+1
| | | | | | | because it's more likely to keep debug line information in its original order. llvm-svn: 108496
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-76/+119
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* Clarify what mysterious check means.Bill Wendling2010-07-091-0/+3
| | | | llvm-svn: 108005
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-119/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-091-76/+119
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Extension of r107506. Make sure that we don't mark a function as having a callBill Wendling2010-07-081-1/+2
| | | | | | if the inline ASM doesn't need a stack frame. llvm-svn: 107922
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-94/+86
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* Fix -fast-isel-abort to check the right instruction.Dan Gohman2010-07-071-1/+1
| | | | llvm-svn: 107839
* Implement bottom-up fast-isel. This has the advantage of not requiringDan Gohman2010-07-071-37/+41
| | | | | | a separate DCE pass over MachineInstrs. llvm-svn: 107804
* Update the insert position after scheduling, which may change theDan Gohman2010-07-071-0/+1
| | | | | | | position when emitting multiple blocks when executing a custom inserter. llvm-svn: 107797
* Give FunctionLoweringInfo an MBB member, avoiding the need to pass itDan Gohman2010-07-071-53/+56
| | | | | | | | around everywhere, and also give it an InsertPt member, to enable isel to operate at an arbitrary position within a block, rather than just appending to a block. llvm-svn: 107791
* Simplify FastISel's constructor by giving it a FunctionLoweringInfoDan Gohman2010-07-071-7/+1
| | | | | | | | | instance, rather than pointers to all of FunctionLoweringInfo's members. This eliminates an NDEBUG ABI sensitivity. llvm-svn: 107789
* Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This willDan Gohman2010-07-071-1/+1
| | | | | | allow target-specific fast-isel code to make use of it directly. llvm-svn: 107787
* CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.Dan Gohman2010-07-061-3/+2
| | | | | | SelectBasicBlock doesn't needs its BasicBlock argument. llvm-svn: 107712
* Proper indentation.Bill Wendling2010-07-041-1/+1
| | | | llvm-svn: 107581
* Propagate the AlignStack bit in InlineAsm's to the Dale Johannesen2010-07-021-0/+1
| | | | | | | | | | | | | | | | | | | PrologEpilog code, and use it to determine whether the asm forces stack alignment or not. gcc consistently does not do this for GCC-style asms; Apple gcc inconsistently sometimes does it for asm blocks. There is no convenient place to put a bit in either the SDNode or the MachineInstr form, so I've added an extra operand to each; unlovely, but it does allow for expansion for more bits, should we need it. PR 5125. Some existing testcases are affected. The operand lists of the SDNode and MachineInstr forms are indexed with awesome mnemonics, like "2"; I may fix this someday, but not now. I'm not making it any worse. If anyone is inspired I think you can find all the right places from this patch. llvm-svn: 107506
* Rename CreateReg to CreateRegs, and MakeReg to CreateReg.Dan Gohman2010-07-021-1/+1
| | | | llvm-svn: 107451
* Temporarily disable on-demand fast-isel.Dan Gohman2010-07-011-0/+2
| | | | llvm-svn: 107393
* Use FuncInfo's isExportedInst accessor method instead ofDan Gohman2010-07-011-1/+1
| | | | | | doing the work manually. llvm-svn: 107384
* Rename CreateRegForValue to CreateReg, and change its argumentDan Gohman2010-07-011-1/+1
| | | | | | | from a Value to a Type, because it doesn't actually care about the Value. llvm-svn: 107383
* Enable on-demand fast-isel.Dan Gohman2010-07-011-0/+6
| | | | llvm-svn: 107377
* Reapply r106634, now that the bug it exposed is fixed.Dan Gohman2010-06-241-99/+1
| | | | llvm-svn: 106746
* Revert r106263, "Fold the ShrinkDemandedOps pass into the regular ↵Daniel Dunbar2010-06-231-1/+99
| | | | | | DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. llvm-svn: 106634
* Minor code simplifications.Dan Gohman2010-06-181-18/+12
| | | | llvm-svn: 106286
* Give NamedRegionTimer an Enabled flag, allowing all its clients toDan Gohman2010-06-181-48/+28
| | | | | | | | | | | | | | | | | | | | switch from this: if (TimePassesIsEnabled) { NamedRegionTimer T(Name, GroupName); do_something(); } else { do_something(); // duplicate the code, this time without a timer! } to this: { NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled); do_something(); } llvm-svn: 106285
* Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,Dan Gohman2010-06-181-99/+1
| | | | | | which is faster, simpler, and less surprising. llvm-svn: 106263
* SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValueDan Gohman2010-05-291-2/+2
| | | | | | | shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set doesn't needs its EnableFastISel argument. llvm-svn: 105101
* Add FIXME comment to remove this.Bill Wendling2010-05-261-0/+2
| | | | llvm-svn: 104749
* Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list ofBill Wendling2010-05-261-21/+24
| | | | | | usual suspects that could "return twice". llvm-svn: 104737
* Update debug info when live-in reg is copied into a vreg.Devang Patel2010-05-261-0/+22
| | | | llvm-svn: 104732
* Move the check for "calls setjmp" to SelectionDAGISel so that it can be used byBill Wendling2010-05-261-0/+32
| | | | | | more than just the stack slot coloring algorithm. llvm-svn: 104722
* Temporarily revert r104655 as it's breaking the bots.Eric Christopher2010-05-261-34/+0
| | | | llvm-svn: 104664
* Dale and Evan suggested putting the "check for setjmp" much earlier in theBill Wendling2010-05-261-0/+34
| | | | | | machine code generation. That's a good idea, so I made it so. llvm-svn: 104655
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-201-2/+4
| | | | | | | | | pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot of long latency instructions so a strict register pressure reduction scheduler does not work well. Early experiments show this speeds up some NEON loops by over 30%. llvm-svn: 104216
* Code refactoring: pull SchedPreference enum from TargetLowering.h to ↵Evan Cheng2010-05-191-3/+3
| | | | | | TargetMachine.h and put it in its own namespace. llvm-svn: 104147
* - Set the "HasCalls" flag after instruction selection is finished.Bill Wendling2010-05-171-13/+19
| | | | | | | - Change the logic DisableFramePointerElim() to check for the -disable-non-leaf-fp-elim before -disable-fp-elim. llvm-svn: 103990
* Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe whatBill Wendling2010-05-141-0/+14
| | | | | | | | | the variable actually tracks. N.B., several back-ends are using "HasCalls" as being synonymous for something that adjusts the stack. This isn't 100% correct and should be looked into. llvm-svn: 103802
* Instruction selection optimizations may have moved the def of a function ↵Evan Cheng2010-05-041-1/+2
| | | | | | argument out of the entry block. rdar://7937489 llvm-svn: 102993
* Remove the code for special-casing byval for fast-isel. SelectionDAGDan Gohman2010-05-011-18/+2
| | | | | | | handles argument lowering anyway, so there's no need for special casing here. llvm-svn: 102828
* Fix whitespace.Dan Gohman2010-05-011-1/+1
| | | | llvm-svn: 102817
* Reorgnaize more switch code lowering to clean up some trickyDan Gohman2010-05-011-21/+22
| | | | | | | | | | | code, and to eliminate the need for the SelectionDAGBuilder state to be live during CodeGenAndEmitDAG calls. Call SDB->clear() before CodeGenAndEmitDAG calls instead of before it, and move the CurDAG->clear() out of SelectionDAGBuilder, which doesn't own the DAG, and into CodeGenAndEmitDAG. llvm-svn: 102814
OpenPOWER on IntegriCloud