| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 108381
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This may not be right in all cases, but it's better
than asserting which it was doing before. PR 7528.
llvm-svn: 108268
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llvm-svn: 108164
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correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
llvm-svn: 108072
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- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
llvm-svn: 108039
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U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
llvm-svn: 107987
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a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
llvm-svn: 107943
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Debug info intrinsics win for now.
llvm-svn: 107850
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a separate DCE pass over MachineInstrs.
llvm-svn: 107804
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a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
llvm-svn: 107800
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allow target-specific fast-isel code to make use of it directly.
llvm-svn: 107787
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code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
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SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
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llvm-svn: 107710
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llvm-svn: 107612
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PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks. There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it. PR 5125. Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now. I'm not making it any
worse. If anyone is inspired I think you can find all
the right places from this patch.
llvm-svn: 107506
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llvm-svn: 107451
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from a Value to a Type, because it doesn't actually care about
the Value.
llvm-svn: 107383
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SelectionDAGBuilder::getValue into a helper function, with fixes to
use DenseMaps safely.
llvm-svn: 107371
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value if the search fails.
llvm-svn: 107368
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this could break something (but doesn't seem to).
llvm-svn: 107295
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llvm-svn: 107279
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llvm-svn: 107127
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for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
llvm-svn: 106893
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is not used. Spotted by gcc-4.6.
llvm-svn: 106854
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llvm-svn: 106836
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which trivially fold away.
llvm-svn: 106765
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case where the bit mask has exactly one bit.
llvm-svn: 106716
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llvm-svn: 106423
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Split the code for materializing a value out of
SelectionDAGBuilder::getValue into a helper function, so that it can
be used in other ways. Add a new getNonRegisterValue function which
uses it, for use in code which doesn't want a CopyFromReg even
when FuncMap.ValueMap already has an entry for it.
llvm-svn: 106422
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llvm-svn: 106279
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Radar 7927666.
llvm-svn: 105285
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llvm-svn: 105105
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shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.
llvm-svn: 105101
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This will help reduce the amount of casting required on 64-bit targets.
llvm-svn: 104911
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llvm-svn: 104897
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llvm-svn: 104869
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ISD::. No functional change.
llvm-svn: 104734
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
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to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
llvm-svn: 103495
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llvm-svn: 103457
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llvm-svn: 103305
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llvm-svn: 103126
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modified.
llvm-svn: 102816
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code, and to eliminate the need for the SelectionDAGBuilder
state to be live during CodeGenAndEmitDAG calls.
Call SDB->clear() before CodeGenAndEmitDAG calls instead of
before it, and move the CurDAG->clear() out of SelectionDAGBuilder,
which doesn't own the DAG, and into CodeGenAndEmitDAG.
llvm-svn: 102814
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llvm-svn: 102810
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llvm-svn: 102661
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entry block.
llvm-svn: 102653
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llvm-svn: 102602
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llvm-svn: 102590
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