summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* finish pushing MachinePointerInfo through selectiondags. At this point,Chris Lattner2010-09-211-6/+7
| | | | | | | I think I've audited all uses, so it should be dependable for address spaces, and the pointer+offset info should also be accurate when there. llvm-svn: 114464
* Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON loadBob Wilson2010-09-211-1/+2
| | | | | | and store intrinsics are represented with MemIntrinsicSDNodes. llvm-svn: 114454
* continue MachinePointerInfo'izing, eliminating use of one of the oldChris Lattner2010-09-211-6/+10
| | | | | | getLoad overloads. llvm-svn: 114443
* reimplement memcpy/memmove/memset lowering to use MachinePointerInfoChris Lattner2010-09-211-5/+7
| | | | | | | instead of srcvalue/offset pairs. This corrects SV info for mem operations whose size is > 32-bits. llvm-svn: 114401
* simplify interface to SelectionDAG::getMemIntrinsicNode, making it take a ↵Chris Lattner2010-09-211-1/+2
| | | | | | MachinePointerInfo llvm-svn: 114397
* chagne interface to SelectionDAG::getAtomic to take a MachinePointerInfo,Chris Lattner2010-09-211-1/+1
| | | | | | eliminating some weird "infer a frame address" logic which was dead. llvm-svn: 114396
* Check bb to ensure that alloca is in separate basic block.Devang Patel2010-09-151-7/+9
| | | | | | This fixes funcargs.exp regression reported by gdb testsuite. llvm-svn: 113992
* If dbg.declare from non-entry block is using alloca from entry block then ↵Devang Patel2010-09-151-2/+14
| | | | | | use offset available in StaticAllocaMap to emit DBG_VALUE. Right now, this has no material impact because varible info also collected using offset table maintained in machine module info. llvm-svn: 113967
* Added skeleton for inline asm multiple alternative constraint support.John Thompson2010-09-131-45/+32
| | | | llvm-svn: 113766
* Detect undef value early and save unnecessary NodeMap query.Devang Patel2010-09-021-0/+11
| | | | llvm-svn: 112864
* Tidy up.Devang Patel2010-09-021-11/+9
| | | | llvm-svn: 112858
* Reapply r112623. Included additional check for unused byval argument.Devang Patel2010-08-311-1/+19
| | | | llvm-svn: 112659
* Revert r112623. It is causing self host build failures.Devang Patel2010-08-311-16/+1
| | | | llvm-svn: 112631
* Remember byval argument's frame index during argument lowering and use this ↵Devang Patel2010-08-311-1/+16
| | | | | | | | info to emit debug info. Fixes Radar 8367011. llvm-svn: 112623
* Offset is not always unsigned number.Devang Patel2010-08-311-1/+1
| | | | llvm-svn: 112584
* remove unions from LLVM IR. They are severely buggy and notChris Lattner2010-08-281-5/+0
| | | | | | being actively maintained, improved, or extended. llvm-svn: 112356
* Completely disable tail calls when fast-isel is enabled, as fast-iselDan Gohman2010-08-281-0/+5
| | | | | | doesn't currently support dealing with this. llvm-svn: 112341
* Simplify.Devang Patel2010-08-271-4/+1
| | | | llvm-svn: 112305
* Revert r112213. It is not needed.Devang Patel2010-08-261-15/+4
| | | | llvm-svn: 112242
* If node is not available then use FuncInfo.ValueMap to emit debug info for ↵Devang Patel2010-08-261-5/+9
| | | | | | byval parameter. llvm-svn: 112238
* Speculatively revert r112207.Devang Patel2010-08-261-3/+1
| | | | llvm-svn: 112216
* 80 col.Devang Patel2010-08-261-1/+2
| | | | llvm-svn: 112215
* Update DanglingDebugInfo so that it can be used to track llvm.dbg.declare also.Devang Patel2010-08-261-4/+15
| | | | llvm-svn: 112213
* Donot forget to resolve dangling debug info in a case where virtual ↵Devang Patel2010-08-261-1/+3
| | | | | | register, used for a value, is initialized after a dbg intrinsic is seen. llvm-svn: 112207
* zap dead code.Chris Lattner2010-08-261-5/+0
| | | | llvm-svn: 112155
* Change handling of illegal vector types to widen when possible instead of Chris Lattner2010-08-251-13/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
* Remove dead argument.Devang Patel2010-08-251-4/+3
| | | | llvm-svn: 112085
* split the vector case of getCopyFromParts out to its own function,Chris Lattner2010-08-241-81/+102
| | | | | | no functionality change. llvm-svn: 111994
* split the vector case out of getCopyToParts into its own function. NoChris Lattner2010-08-241-117/+126
| | | | | | functionality change. llvm-svn: 111990
* Handle Values with no value in getCopyFromRegs.Dan Gohman2010-07-261-0/+4
| | | | llvm-svn: 109415
* Propagate alloca alignment information via variable size object frameEric Christopher2010-07-171-1/+1
| | | | | | | | information. No functional change yet. llvm-svn: 108583
* Revert r108369, sorting llvm.dbg.declare information by source position,Dan Gohman2010-07-161-14/+0
| | | | | | | | | | | | | since it doesn't work for front-ends which don't emit column information (which includes llvm-gcc in its present configuration), and doesn't work for clang for K&R style variables where the variables are declared in a different order from the parameter list. Instead, make a separate pass through the instructions to collect the llvm.dbg.declare instructions in order. This ensures that the debug information for variables is emitted in this order. llvm-svn: 108538
* The SelectionDAGBuilder's handling of debug info, on rareDale Johannesen2010-07-161-12/+38
| | | | | | | | | | occasions, caused code to be generated in a different order. All cases I've seen involved float softening in the type legalizer, and this could be perhaps be fixed there, but it's better not to generate things differently in the first place. 7797940 (6/29/2010..7/15/2010). llvm-svn: 108484
* Revert. This isn't the correct way to go.Bill Wendling2010-07-151-14/+0
| | | | llvm-svn: 108478
* Handle code gen for the unreachable instruction if it's the only instruction inBill Wendling2010-07-151-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the function. We'll just turn it into a "trap" instruction instead. The problem with not handling this is that it might generate a prologue without the equivalent epilogue to go with it: $ cat t.ll define void @foo() { entry: unreachable } $ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables .section __TEXT,__text,regular,pure_instructions .globl _foo .align 4, 0x90 _foo: ## @foo Leh_func_begin0: ## BB#0: ## %entry pushq %rbp Ltmp0: movq %rsp, %rbp Ltmp1: Leh_func_end0: ... The unwind tables then have bad data in them causing all sorts of problems. Fixes <rdar://problem/8096481>. llvm-svn: 108473
* 80-col.Eric Christopher2010-07-141-2/+3
| | | | llvm-svn: 108381
* In inline asm treat indirect 'X' constraint as 'm'.Dale Johannesen2010-07-131-3/+5
| | | | | | | This may not be right in all cases, but it's better than asserting which it was doing before. PR 7528. llvm-svn: 108268
* Fix a typo and fit in 80 columns. Found by Bob Wilson.Rafael Espindola2010-07-121-1/+2
| | | | llvm-svn: 108164
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-111-1/+2
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-91/+22
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-22/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-091-91/+22
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-22/+91
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* Implement bottom-up fast-isel. This has the advantage of not requiringDan Gohman2010-07-071-17/+12
| | | | | | a separate DCE pass over MachineInstrs. llvm-svn: 107804
* Add X86FastISel support for return statements. This entails refactoringDan Gohman2010-07-071-74/+10
| | | | | | | a bunch of stuff, to allow the target-independent calling convention logic to be employed. llvm-svn: 107800
* Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This willDan Gohman2010-07-071-1/+1
| | | | | | allow target-specific fast-isel code to make use of it directly. llvm-svn: 107787
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-071-5/+12
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.Dan Gohman2010-07-061-2/+3
| | | | | | SelectBasicBlock doesn't needs its BasicBlock argument. llvm-svn: 107712
* Propagate debug loc.Devang Patel2010-07-061-1/+1
| | | | llvm-svn: 107710
* random tidyingChris Lattner2010-07-051-6/+8
| | | | llvm-svn: 107612
OpenPOWER on IntegriCloud