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path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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* Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames2012-02-141-1/+1
| | | | | | consistency with setExceptionPointerRegister(...). llvm-svn: 150460
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-0/+6
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* [unwind removal] Remove all of the code for the dead 'unwind' instruction. ThereBill Wendling2012-02-061-3/+0
| | | | | | | were no 'unwind' instructions being generated before this, so this is in effect a no-op. llvm-svn: 149906
* SwitchInst refactoring.Stepan Dyatkovskiy2012-02-011-6/+6
| | | | | | | | | | | | | | | | | The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. llvm-svn: 149481
* Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.Bill Wendling2012-01-311-37/+0
| | | | llvm-svn: 149331
* continue making the world safe for ConstantDataVector. At this point,Chris Lattner2012-01-271-1/+1
| | | | | | | we should (theoretically optimize and codegen ConstantDataVector as well as ConstantVector. llvm-svn: 149116
* eliminate the Constant::getVectorElements method. There are better (andChris Lattner2012-01-261-13/+4
| | | | | | | more robust) ways to do what it was doing now. Also, add static methods for decoding a ShuffleVector mask. llvm-svn: 149028
* Use the right method to get the # elements in a CDS.Chris Lattner2012-01-251-1/+1
| | | | llvm-svn: 148897
* add more support for ConstantDataSequentialChris Lattner2012-01-241-2/+19
| | | | llvm-svn: 148802
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-5/+1
| | | | llvm-svn: 148578
* Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper2012-01-171-2/+3
| | | | | | checked for legalisation llvm-svn: 148275
* Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper2012-01-161-1/+1
| | | | | | arithmetic so should not be checked in legalisation llvm-svn: 148228
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner2012-01-031-9/+21
| | | | | | | | | | | | | | | | | | Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. llvm-svn: 147502
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak2011-12-201-2/+2
| | | | llvm-svn: 146986
* Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. ↵Owen Anderson2011-12-151-0/+22
| | | | | | These are already marked as illegal by default. llvm-svn: 146623
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson2011-12-081-13/+34
| | | | | | can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. llvm-svn: 146193
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-081-0/+47
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* Add support for vectors of pointers.Nadav Rotem2011-12-051-1/+1
| | | | llvm-svn: 145801
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-8/+12
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Remove dead llvm.eh.sjlj.dispatchsetup intrinsic.Bill Wendling2011-11-281-5/+0
| | | | llvm-svn: 145263
* Fix an obvious omission in the SelectionDAGBuilder where we wereChandler Carruth2011-11-221-2/+2
| | | | | | | | | | | | | dropping weights on the floor for invokes. This was impeding my writing further test cases for invoke when interacting with probabilities and block placement. No test case as there doesn't appear to be a way to test this stuff. =/ Suggestions for a test case of course welcome. I hope to be able to add test cases that indirectly cover this eventually by adding probabilities to the exceptional edge and reordering blocks as a result. llvm-svn: 145060
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-151-1/+0
| | | | llvm-svn: 144634
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-3/+5
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Don't use floating point to do an integer's job.Jakob Stoklund Olesen2011-10-261-4/+7
| | | | | | | | | | | This code makes different decisions when compiled into x87 instructions because of different rounding behavior. That caused phase 2/3 miscompares on 32-bit Linux when the phase 1 compiler was built with gcc (using x87), and the phase 2 compiler was built with clang (using SSE). This fixes PR11200. llvm-svn: 143006
* Fix a bunch of unused variable warnings when doing a releaseDuncan Sands2011-10-181-1/+1
| | | | | | build with gcc-4.6. llvm-svn: 142350
* Fix comment to refer to correct instructionHal Finkel2011-10-181-1/+1
| | | | llvm-svn: 142334
* Clear out the landing pad to call site map for each function.Bill Wendling2011-10-151-0/+1
| | | | | | | This isn't put into the 'clear()' method because the information needs to stick around (at least for a little bit) after the selection DAG is built. llvm-svn: 142032
* Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen2011-10-121-0/+12
| | | | | | | | | | | | | The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. llvm-svn: 141833
* Use a utility from MathExtras to clarify a check and avoid undefined ↵Eli Friedman2011-10-121-1/+1
| | | | | | behavior. Based on patch by Ahmed Charles. llvm-svn: 141829
* Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling2011-10-071-2/+8
| | | | | | do. This will be useful later on with the new SJLJ stuff. llvm-svn: 141416
* Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman2011-10-061-66/+0
| | | | | | with this patch. llvm-svn: 141333
* Modify the mapping from landing pad to call sites to accept more than one callBill Wendling2011-10-051-1/+1
| | | | | | site. llvm-svn: 141226
* Create a mapping between the landing pad basic block and the call site index ↵Bill Wendling2011-10-041-0/+2
| | | | | | for later use. llvm-svn: 141125
* Promote comment to doxycomment. Adjust whitespace. No functionality change.Nick Lewycky2011-09-301-4/+3
| | | | llvm-svn: 140899
* Clean up uses of switch instructions so they are not dependent on the ↵Eli Friedman2011-09-291-2/+2
| | | | | | operand ordering. Patch by Stepan Dyatkovskiy. llvm-svn: 140803
* Use the local we already set up.Eric Christopher2011-09-291-1/+1
| | | | llvm-svn: 140745
* Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.Bill Wendling2011-09-281-1/+2
| | | | llvm-svn: 140678
* Create and use an llvm.eh.sjlj.functioncontext intrinsic.Bill Wendling2011-09-281-0/+8
| | | | | | | | This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. llvm-svn: 140676
* Fix check for unaligned load/store so it doesn't catch over-aligned load/store.Eli Friedman2011-09-131-2/+2
| | | | llvm-svn: 139649
* Error out on CodeGen of unaligned load/store. Fix test so it isn't ↵Eli Friedman2011-09-131-2/+9
| | | | | | accidentally testing that case. llvm-svn: 139641
* tidy up a bitChris Lattner2011-09-091-7/+5
| | | | llvm-svn: 139419
* Directly point debug info to the stack slot of the arugment, instead of ↵Devang Patel2011-09-081-15/+17
| | | | | | trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. llvm-svn: 139330
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-2/+4
| | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
* Split the init.trampoline intrinsic, which currently combines GCC'sDuncan Sands2011-09-061-5/+8
| | | | | | | | | | | | | | | | | | | | init.trampoline and adjust.trampoline intrinsics, into two intrinsics like in GCC. While having one combined intrinsic is tempting, it is not natural because typically the trampoline initialization needs to be done in one function, and the result of adjust trampoline is needed in a different (nested) function. To get around this llvm-gcc hacks the nested function lowering code to insert an additional parent variable holding the adjust.trampoline result that can be accessed from the child function. Dragonegg doesn't have the luxury of tweaking GCC code, so it stored the result of adjust.trampoline in the memory GCC set aside for the trampoline itself (this is always available in the child function), and set up some new memory (using an alloca) to hold the trampoline. Unfortunately this breaks Go which allocates trampoline memory on the heap and wants to use it even after the parent has exited (!). Rather than doing even more hacks to get Go working, it seemed best to just use two intrinsics like in GCC. Patch mostly by Sanjoy Das. llvm-svn: 139140
* Atomic load/store on ARM/Thumb.Eli Friedman2011-08-261-5/+1
| | | | | | | | | | | | I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
* Basic x86 code generation for atomic load and store instructions.Eli Friedman2011-08-241-8/+81
| | | | llvm-svn: 138478
* Fix 80 col violations.Evan Cheng2011-08-231-2/+4
| | | | llvm-svn: 138356
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