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path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-251-1/+3
| | | | | | intrinisic. llvm-svn: 124203
* Speculatively revert r124138.Devang Patel2011-01-241-3/+1
| | | | llvm-svn: 124142
* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-241-1/+3
| | | | | | intrinisic. llvm-svn: 124138
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-2/+2
| | | | | | and fixes here and there. llvm-svn: 123170
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-1/+1
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Use an IndexedMap for LiveOutRegInfo to hide its dependence on ↵Jakob Stoklund Olesen2011-01-081-6/+3
| | | | | | TargetRegisterInfo::FirstVirtualRegister. llvm-svn: 123096
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-3/+8
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson2011-01-071-1/+1
| | | | | | | | | | | | | | | Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. llvm-svn: 122995
* Avoid zero extend bit test operands to pointer type if all the masks fit inEvan Cheng2011-01-061-19/+33
| | | | | | | the original type of the switch statement key. rdar://8781238 llvm-svn: 122935
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* reduce indentation by using continue, no functionality change.Chris Lattner2010-12-131-38/+41
| | | | llvm-svn: 121662
* PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad2010-12-071-2/+1
| | | | | | | | zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG ↵Devang Patel2010-12-061-19/+12
| | | | | | message instead of creating DBG_VALUE for undefined value in reg0. llvm-svn: 121059
* add TLI support indicating that jumps are more expensive than logical operationsChris Lattner2010-11-301-1/+3
| | | | | | and use this to disable a specific optimization. Patch by Micah Villmow! llvm-svn: 120435
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-45/+45
| | | | llvm-svn: 119990
* Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization.Benjamin Kramer2010-11-221-1/+47
| | | | | | | This currently only catches the most basic case, a two-case switch, but can be extended later. llvm-svn: 119964
* Removing the useless test that I added recently. It was meant as an example, ↵Andrew Trick2010-11-201-3/+6
| | | | | | but not complicated enough to merit another test. llvm-svn: 119898
* Bug 8621 fix - pointer cast stripped from inline asm constraint argument.John Thompson2010-11-171-3/+0
| | | | llvm-svn: 119590
* typo (4th checkin for one fix)Andrew Trick2010-11-121-1/+1
| | | | llvm-svn: 118913
* Fixes PR8287: SD scheduling time. The fix is a failsafe that preventsAndrew Trick2010-11-121-13/+53
| | | | | | | | | catastrophic compilation time in the event of unreasonable LLVM IR. Code quality is a separate issue--someone upstream needs to do a better job of reducing to llvm.memcpy. If the situation can be reproduced with any supported frontend, then it will be a separate bug. llvm-svn: 118904
* tidy up.Chris Lattner2010-11-121-7/+5
| | | | llvm-svn: 118896
* Remove the memmove->memcpy optimization from CodeGen. MemCpyOpt does this.Dan Gohman2010-11-111-14/+0
| | | | llvm-svn: 118789
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-3/+3
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* If value map does not have register for an argument then try to find frame ↵Devang Patel2010-11-021-5/+8
| | | | | | index before giving up. llvm-svn: 118022
* Use frameindex, if available, as a last resort to emit debug info for a ↵Devang Patel2010-11-021-2/+13
| | | | | | parameter. llvm-svn: 118020
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-291-2/+4
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Use a MemIntrinsicSDNode for ISD::PREFETCH, which touchesDale Johannesen2010-10-261-2/+10
| | | | | | | | memory, so a MachineMemOperand is useful (not propagated into the MachineInstr yet). No functional change except for dump output. llvm-svn: 117413
* Assign source ordering to nodes created for StoreInst.Devang Patel2010-10-261-2/+5
| | | | llvm-svn: 117404
* X86: Base _fltused on the FunctionType of the called value instead of the ↵Michael J. Spencer2010-10-211-19/+20
| | | | | | | | potentially null "CalledFunction". Thanks Duncan! This is needed for indirect calls. llvm-svn: 117061
* CodeGen-Windows: Only emit _fltused if a VarArg function is called with ↵Michael J. Spencer2010-10-211-5/+5
| | | | | | | | floating point args. This should be the minimum set of functions that could possibly need it. llvm-svn: 116978
* Make CodeGen TBAA-aware.Dan Gohman2010-10-201-3/+6
| | | | llvm-svn: 116890
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-191-2/+6
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 llvm-svn: 116879
* X86-Windows: Emit an undefined global __fltused symbol when targeting WindowsMichael J. Spencer2010-10-161-0/+20
| | | | | | if any floating point arguments are passed to an external function. llvm-svn: 116665
* Whitespace!Michael J. Spencer2010-10-161-46/+46
| | | | llvm-svn: 116664
* ComputeLinearIndex doesn't need its TLI argument.Dan Gohman2010-10-061-4/+2
| | | | llvm-svn: 115792
* Fix code gen crash reported in PR 8235. We still lose debug info for the ↵Devang Patel2010-10-011-0/+3
| | | | | | unused argument here. This is a known limitation recorded debuginfo-tests/trunk/dbg-declare2.ll function 'f6' test case. llvm-svn: 115323
* typoGabor Greif2010-10-011-1/+1
| | | | llvm-svn: 115310
* fix typoChris Lattner2010-10-011-1/+1
| | | | llvm-svn: 115300
* Massive rewrite of MMX: Dale Johannesen2010-09-301-0/+60
| | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
* When isel is emitting instructions for an x86 target without CMOV, the CFG isJakob Stoklund Olesen2010-09-301-0/+13
| | | | | | | | | | | | | | | | | edited during emission. If the basic block ends in a switch that gets lowered to a jump table, any phis at the default edge were getting updated wrong. The jump table data structure keeps a pointer to the header blocks that wasn't getting updated after the MBB is split. This bug was exposed on 32-bit Linux when disabling critical edge splitting in codegen prepare. The fix is to uipdate stale MBB pointers whenever a block is split during emission. llvm-svn: 115191
* Fix for test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll crash.John Thompson2010-09-241-0/+20
| | | | llvm-svn: 114767
* Get rid of pop_macro warnings on MSVC.Michael J. Spencer2010-09-241-3/+5
| | | | llvm-svn: 114750
* Revert 114634 for now since buildbot claim it broke Clang self-hosting. I ↵Evan Cheng2010-09-231-4/+6
| | | | | | doubt it but it's possible it's exposing another bug somewhere. llvm-svn: 114681
* Follow up to r114630. Do not optimize away unconditional branch following a ↵Evan Cheng2010-09-231-6/+4
| | | | | | conditional one. llvm-svn: 114634
* SDISel should not optimize a unconditional branch following a conditional branchEvan Cheng2010-09-231-4/+5
| | | | | | | | | | | | when the unconditional branch destination is the fallthrough block. The canonicalization makes it easier to allow optimizations on DAGs to invert conditional branches. The branch folding pass (and AnalyzeBranch) will clean up the unnecessary unconditional branches later. This is one of the patches leading up to disabling codegen prepare critical edge splitting. llvm-svn: 114630
* finish pushing MachinePointerInfo through selectiondags. At this point,Chris Lattner2010-09-211-6/+7
| | | | | | | I think I've audited all uses, so it should be dependable for address spaces, and the pointer+offset info should also be accurate when there. llvm-svn: 114464
* Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON loadBob Wilson2010-09-211-1/+2
| | | | | | and store intrinsics are represented with MemIntrinsicSDNodes. llvm-svn: 114454
* continue MachinePointerInfo'izing, eliminating use of one of the oldChris Lattner2010-09-211-6/+10
| | | | | | getLoad overloads. llvm-svn: 114443
* reimplement memcpy/memmove/memset lowering to use MachinePointerInfoChris Lattner2010-09-211-5/+7
| | | | | | | instead of srcvalue/offset pairs. This corrects SV info for mem operations whose size is > 32-bits. llvm-svn: 114401
* simplify interface to SelectionDAG::getMemIntrinsicNode, making it take a ↵Chris Lattner2010-09-211-1/+2
| | | | | | MachinePointerInfo llvm-svn: 114397
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