summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Adding more assignment of ordering to SDNodes. This time in the "call" andBill Wendling2009-12-221-32/+66
| | | | | | generic copy functions. llvm-svn: 91872
* Add ordering of SDNodes to LowerCallTo.Bill Wendling2009-12-221-19/+44
| | | | llvm-svn: 91866
* Now add ordering to SDNodes created by the massive intrinsic lowering function.Bill Wendling2009-12-221-100/+183
| | | | llvm-svn: 91863
* To make things interesting, I added MORE code to set the ordering ofBill Wendling2009-12-221-32/+387
| | | | | | SDNodes. This time in the load/store and limited-precision code. llvm-svn: 91860
* Add more plumbing to assign ordering to SDNodes. Have the "getValue" methodBill Wendling2009-12-211-59/+133
| | | | | | | assign the ordering when called. Combine some of the ordering assignments to keep things simple. llvm-svn: 91857
* More ordering plumbing. This time for GEP. I need to remember to assignBill Wendling2009-12-211-4/+32
| | | | | | orderings to values returned by getValue(). llvm-svn: 91850
* Another incremental check-in for assigning ordering to SDNodes. This time forBill Wendling2009-12-211-25/+75
| | | | | | shuffle and insert vector. llvm-svn: 91847
* Assign ordering to more instructions. Incremental check-in.Bill Wendling2009-12-211-57/+156
| | | | llvm-svn: 91846
* - Add a bit more plumbing assigning an order to SDNodes.Bill Wendling2009-12-211-8/+15
| | | | | | - Modify the "dump" method to emit the order of an SDNode. llvm-svn: 91845
* First wave of plumbing for assigning an ordering to SDNodes. This takes care ofBill Wendling2009-12-211-28/+43
| | | | | | a lot of the branching instructions. llvm-svn: 91838
* Changes from review:Bill Wendling2009-12-181-3/+8
| | | | | | | | | | | - Move DisableScheduling flag into TargetOption.h - Move SDNodeOrdering into its own header file. Give it a minimal interface that doesn't conflate construction with storage. - Move assigning the ordering into the SelectionDAGBuilder. This isn't used yet, so there should be no functional changes. llvm-svn: 91727
* Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson2009-12-181-1/+1
| | | | | | | | The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. llvm-svn: 91649
* Fix a comment grammaro.Bob Wilson2009-12-171-2/+2
| | | | llvm-svn: 91584
* Reapply r91392, it was only unmasking the bug, and since TOT is still broken ↵Daniel Dunbar2009-12-161-0/+3
| | | | | | having it reverted does no good. llvm-svn: 91560
* Revert "Initial work on disabling the scheduler. This is a work in progress, andDaniel Dunbar2009-12-161-3/+0
| | | | | | | this", this broke llvm-gcc bootstrap for release builds on x86_64-apple-darwin10. llvm-svn: 91533
* Initial work on disabling the scheduler. This is a work in progress, and thisBill Wendling2009-12-151-0/+3
| | | | | | | | | | | | | | | stuff isn't used just yet. We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2' flags. The hypothesis is that the people who use these flags know what they are doing, and have hand-optimized the C code to reduce latencies and other conflicts. The idea behind our scheme to turn off scheduling is to create a map "on the side" during DAG generation. It will order the nodes by how they appeared in the code. This map is then used during scheduling to get the ordering. llvm-svn: 91392
* Fix the result type of SELECT nodes lowered from Select instructions withDan Gohman2009-12-111-1/+1
| | | | | | aggregate return values. This fixes PR5754. llvm-svn: 91145
* Rename SelectionDAGLowering to SelectionDAGBuilder, and renameDan Gohman2009-11-231-0/+5821
SelectionDAGBuild.cpp to SelectionDAGBuilder.cpp. llvm-svn: 89681
OpenPOWER on IntegriCloud