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* TargetLowering: Add getVectorIdxTy() function v2Tom Stellard2013-08-051-16/+20
| | | | | | | | | | | | | | | | | | | | | This virtual function can be implemented by targets to specify the type to use for the index operand of INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT, INSERT_SUBVECTOR, EXTRACT_SUBVECTOR. The default implementation returns the result from TargetLowering::getPointerTy() The previous code was using TargetLowering::getPointerTy() for vector indices, because this is guaranteed to be legal on all targets. However, using TargetLowering::getPointerTy() can be a problem for targets with pointer sizes that differ across address spaces. On such targets, when vectors need to be loaded or stored to an address space other than the default 'zero' address space (which is the address space assumed by TargetLowering::getPointerTy()), having an index that is a different size than the pointer can lead to inefficient pointer calculations, (e.g. 64-bit adds for a 32-bit address space). There is no intended functionality change with this patch. llvm-svn: 187748
* Fix crashing on invalid inline asm with matching constraints.Eric Christopher2013-07-311-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For a testcase like the following: typedef unsigned long uint64_t; typedef struct { uint64_t lo; uint64_t hi; } blob128_t; void add_128_to_128(const blob128_t *in, blob128_t *res) { asm ("PAND %1, %0" : "+Q"(*res) : "Q"(*in)); } where we'll fail to allocate the register for the output constraint, our matching input constraint will not find a register to match, and could try to search past the end of the current operands array. On the idea that we'd like to attempt to keep compilation going to find more errors in the module, change the error cases when we're visiting inline asm IR to return immediately and avoid trying to create a node in the DAG. This leaves us with only a single error message per inline asm instruction, but allows us to safely keep going in the general case. llvm-svn: 187470
* Reflow this to be easier to read.Eric Christopher2013-07-301-7/+5
| | | | llvm-svn: 187459
* Document a known limitation of the status quo.Adrian Prantl2013-07-101-1/+3
| | | | llvm-svn: 185992
* Reapply an improved version of r180816/180817.Adrian Prantl2013-07-091-3/+7
| | | | | | | | | | | | | | | Change the informal convention of DBG_VALUE machine instructions so that we can express a register-indirect address with an offset of 0. The old convention was that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain register values the combination reg, reg is used. MachineInstrBuilder::BuildMI knows how to build the new DBG_VALUES. rdar://problem/13658587 llvm-svn: 185966
* AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and allStephen Lin2013-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in order to resolve the following issues with fmuladd (i.e. optional FMA) intrinsics: 1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd intrinsics even if the subtarget does not support FMA instructions, leading to laughably bad code generation in some situations. 2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128, resulting in a call to a software fp128 FMA implementation. 3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize, etc. to types that support hardware FMAs. The function has also been slightly renamed for consistency and to force a merge/build conflict for any out-of-tree target implementing it. To resolve, see comments and fixed in-tree examples. llvm-svn: 185956
* Remove trailing whitespace from SelectionDAG/*.cppStephen Lin2013-07-081-15/+15
| | | | llvm-svn: 185780
* SelectionDAGBuilder: style fixes (add space between end parentheses and open ↵Stephen Lin2013-07-061-10/+10
| | | | | | brace) llvm-svn: 185768
* Stop putting operations after a tail call.Tim Northover2013-07-061-0/+4
| | | | | | | | This prevents the emission of DAG-generated vreg definitions after a tail call be dropping them entirely (on the grounds that nothing could use them anyway, and they interfere with O0 CodeGen). llvm-svn: 185754
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-041-22/+14
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185617
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-14/+22
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-031-22/+14
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185595
* Use SmallVectorImpl instead of SmallVector for iterators and references to ↵Craig Topper2013-07-031-2/+2
| | | | | | avoid specifying the vector size unnecessarily. llvm-svn: 185512
* Debug Info: clean up usage of Verify.Manman Ren2013-06-281-2/+8
| | | | | | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. For cases where we know the type of a DI metadata, use assert. Also update testing cases to make them conform to the format of DI classes. llvm-svn: 185135
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-179/+218
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* During SelectionDAG building explicitly set a node to constant zero when theQuentin Colombet2013-06-181-0/+8
| | | | | | | | | | | | value is zero. This allows optmizations to kick in more easily. Fix some test cases so that they remain meaningful (i.e., not completely dead coded) when optimizations apply. <rdar://problem/14096009> superfluous multiply by high part of zero-extended value. llvm-svn: 184222
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-161-19/+20
| | | | | | | | | | | | | | | | | | | | Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. llvm-svn: 184066
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-16/+16
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Convert sqrt functions into sqrt instructions when -ffast-math is in effect.Preston Gurd2013-05-271-0/+3
| | | | | | | | | | | | When -ffast-math is in effect (on Linux, at least), clang defines __FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the preprocessor to include <bits/math-finite.h>, which renames the sqrt functions. For instance, "sqrt" is renamed as "__sqrt_finite". This patch adds the 3 new names in such a way that they will be treated as equivalent to their respective original names. llvm-svn: 182739
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-251-39/+2
| | | | | | | Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. llvm-svn: 182704
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-219/+220
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Track IR ordering of SelectionDAG nodes 1/4.Andrew Trick2013-05-251-3/+3
| | | | | | | | Use a field in the SelectionDAGNode object to track its IR ordering. This adds fields and utility classes without changing existing interfaces or functionality. llvm-svn: 182701
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-1/+1
| | | | llvm-svn: 182680
* Unify formatting of debug output.Adrian Prantl2013-05-221-1/+1
| | | | llvm-svn: 182495
* Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.Justin Holewinski2013-05-211-0/+5
| | | | | | | | | | The intrinsic calls are dropped, but the annotated value is propagated. Fixes PR 15253 Original patch by Zeng Bin! llvm-svn: 182387
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-6/+9
| | | | llvm-svn: 182180
* Generate debug info for by-value struct args even if they are not used.Adrian Prantl2013-05-161-1/+7
| | | | | | radar://problem/13865940 llvm-svn: 182062
* [inline asm] Return an undef SDValue of the expected value type, rather thanChad Rosier2013-05-011-1/+1
| | | | | | | | | report a fatal error. This allows us to continue processing the translation unit. Test case to come on the clang side because we need an inline asm diagnostics handler in place. rdar://13446483 llvm-svn: 180873
* Only pass 'returned' to target-specific lowering code when the value of ↵Stephen Lin2013-04-301-24/+42
| | | | | | entire register is guaranteed to be preserved. llvm-svn: 180825
* Temporarily revert "Change the informal convention of DBG_VALUE so that we ↵Adrian Prantl2013-04-301-3/+2
| | | | | | | | | | can express a" because it breaks some buildbots. This reverts commit 180816. llvm-svn: 180819
* Change the informal convention of DBG_VALUE so that we can express aAdrian Prantl2013-04-301-2/+3
| | | | | | | | | | | | register-indirect address with an offset of 0. It used to be that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain registers use the combination reg, reg. rdar://problem/13658587 llvm-svn: 180816
* [inline asm] Fix a crasher for an invalid value type/register class.Chad Rosier2013-04-241-4/+11
| | | | | | rdar://13731657 llvm-svn: 180226
* Add CodeGen support for functions that always return arguments via a new ↵Stephen Lin2013-04-201-7/+11
| | | | | | parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). llvm-svn: 179925
* Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson2013-03-231-1/+0
| | | | | | | | | | @llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. llvm-svn: 177820
* Revert r176154 in favor of a better approach.Bill Wendling2013-03-081-7/+0
| | | | | | | | | | | | | | | | | | | Code generation makes some basic assumptions about the IR it's been given. In particular, if there is only one 'invoke' in the function, then that invoke won't be going away. However, with the advent of the `llvm.donothing' intrinsic, those invokes may go away. If all of them go away, the landing pad no longer has any users. This confuses the back-end, which asserts. This happens with SjLj exceptions, because that's the model that modifies the IR based on there being invokes, etc. in the function. Remove any invokes of `llvm.donothing' during SjLj EH preparation. This will give us a CFG that the back-end won't be confused about. If all of the invokes in a function are removed, then the SjLj EH prepare pass won't insert the bogus code the relies upon the invokes being there. <rdar://problem/13228754&13316637> llvm-svn: 176677
* Generate an error message instead of asserting or segfaulting when we can'tChad Rosier2013-03-011-0/+1
| | | | | | | handle indirect register inputs. rdar://13322011 llvm-svn: 176367
* Fix PR10475Michael Liao2013-03-011-1/+1
| | | | | | | | | | | | | | - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. llvm-svn: 176364
* A small refactoring + adding comments.Eli Bendersky2013-02-281-3/+1
| | | | | | | | | | | SelectionDAGIsel::LowerArguments needs a function, not a basic block. So it makes sense to pass it the function instead of extracting a basic-block from the function and then tossing it. This is also more self-documenting (functions have arguments, BBs don't). In addition, added comments to a couple of Select* methods. llvm-svn: 176305
* SelectionDAG: If llvm.donothing has a landingpad, we should clearManman Ren2013-02-271-0/+7
| | | | | | | | | CurrentCallSite to avoid an assertion failure: assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); rdar://problem/13228754 llvm-svn: 176154
* 'Hexadecimal' has two 'a's and only one 'i'.Matt Beaumont-Gay2013-02-251-2/+2
| | | | llvm-svn: 176031
* Fix the root cause of PR15348 by correctly handling alignment 0 onChandler Carruth2013-02-251-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | memory intrinsics in the SDAG builder. When alignment is zero, the lang ref says that *no* alignment assumptions can be made. This is the exact opposite of the internal API contracts of the DAG where alignment 0 indicates that the alignment can be made to be anything desired. There is another, more explicit alignment that is better suited for the role of "no alignment at all": an alignment of 1. Map the intrinsic alignment to this early so that we don't end up generating aligned DAGs. It is really terrifying that we've never seen this before, but we suddenly started generating a large number of alignment 0 memcpys due to the new code to do memcpy-based copying of POD class members. That patch contains a bug that rounds bitfield alignments down when they are the first field. This can in turn produce zero alignments. This fixes weird crashes I've seen in library users of LLVM on 32-bit hosts, etc. llvm-svn: 176022
* Remove unnecessary code.Evan Cheng2013-02-111-4/+0
| | | | llvm-svn: 174854
* Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.Bob Wilson2013-02-081-2/+1
| | | | | | | | | | | | Aside from the question of whether we report a warning or an error when we can't satisfy a requested stack object alignment, the current implementation of this is not good. We're not providing any source location in the diagnostics and the current warning is not connected to any warning group so you can't control it. We could improve the source location somewhat, but we can do a much better job if this check is implemented in the front-end, so let's do that instead. <rdar://problem/13127907> llvm-svn: 174741
* Tweak check to avoid integer overflow (for insanely large alignments)Evan Cheng2013-02-061-2/+2
| | | | llvm-svn: 174482
* Fix errant fallthrough in the generation of the lifetime markers.Nadav Rotem2013-02-011-0/+1
| | | | | | Found by Alexander Kornienko. llvm-svn: 174207
* Make APFloat constructor require explicit semantics.Tim Northover2013-01-221-1/+2
| | | | | | | | | Previously we tried to infer it from the bit width size, with an added IsIEEE argument for the PPC/IEEE 128-bit case, which had a default value. This default value allowed bugs to creep in, where it was inappropriate. llvm-svn: 173138
* Remove unused parameter. Also use the AttributeSet query methods instead of ↵Bill Wendling2013-01-181-2/+1
| | | | | | the Attribute query methods. llvm-svn: 172852
* For inline asm:Eric Christopher2013-01-111-0/+6
| | | | | | | | | | | - recognize string "{memory}" in the MI generation - mark as mayload/maystore when there's a memory clobber constraint. PR14859. Patch by Krzysztof Parzyszek llvm-svn: 172228
* Remove unneeded includes from FunctionLoweringInfo.h.Jakub Staszak2013-01-101-1/+1
| | | | llvm-svn: 172123
* Stack Alignment: throw error if we can't satisfy the minimal alignmentManman Ren2013-01-101-1/+2
| | | | | | | | | | | | | | | | | | requirement when creating stack objects in MachineFrameInfo. Add CreateStackObjectWithMinAlign to throw error when the minimal alignment can't be achieved and to clamp the alignment when the preferred alignment can't be achieved. Same is true for CreateVariableSizedObject. Will not emit error in CreateSpillStackObject or CreateStackObject. As long as callers of CreateStackObject do not assume the object will be aligned at the requested alignment, we should not have miscompile since later optimizations which look at the object's alignment will have the correct information. rdar://12713765 llvm-svn: 172027
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