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* [DAG] Fix incorrect alignment of ext load.Nirav Dave2016-09-221-1/+1
| | | | | | | | | | | | Correctly use alignment size from loaded size not output value size. Reviewers: jyknight, tstellarAMD, arsenm Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23356 llvm-svn: 282177
* [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 ↵Craig Topper2016-09-181-1/+2
| | | | | | | | rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision. Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future. llvm-svn: 281868
* [X86][SSE] Improve recognition of uitofp conversions that can be performed ↵Simon Pilgrim2016-09-181-4/+0
| | | | | | | | | | | | | | as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-3/+3
| | | | llvm-svn: 281495
* getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCISanjay Patel2016-09-141-11/+9
| | | | llvm-svn: 281493
* getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits() ; NFCISanjay Patel2016-09-141-7/+5
| | | | llvm-svn: 281490
* getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-18/+18
| | | | llvm-svn: 281489
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-111-2/+4
| | | | | | | | | | | | | | | | | | | Summary: An IR load can be invariant, dereferenceable, neither, or both. But currently, MI's notion of invariance is IR-invariant && IR-dereferenceable. This patch splits up the notions of invariance and dereferenceability at the MI level. It's NFC, so adds some probably-unnecessary "is-dereferenceable" checks, which we can remove later if desired. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23371 llvm-svn: 281151
* [SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and ↵Simon Pilgrim2016-09-081-0/+20
| | | | | | | | | | | | SimplifyDemandedBits Add the ability to computeKnownBits and SimplifyDemandedBits to extract the known zero/one bits from BUILD_VECTOR, returning the known bits that are shared by every vector element. This is an initial step towards determining the sign bits of a vector (PR29079). Differential Revision: https://reviews.llvm.org/D24253 llvm-svn: 280927
* [SelectionDAG] Simplify extract_subvector( insert_subvector ( Vec, In, Idx ↵Simon Pilgrim2016-09-061-0/+6
| | | | | | | | | | | | ), Idx ) -> In If we are extracting a subvector that has just been inserted then we should just use the original inserted subvector. This has come up in certain several x86 shuffle lowering cases where we are crossing 128-bit lanes. Differential Revision: https://reviews.llvm.org/D24254 llvm-svn: 280715
* Propagate TBAA info in SelectionDAG::getIndexedLoadKrzysztof Parzyszek2016-08-291-1/+2
| | | | | | Patch by Pranav Bhandarkar. llvm-svn: 279998
* [SelectionDAG] Use a union of bitfield structs for SDNode::SubclassData.Justin Lebar2016-08-231-43/+18
| | | | | | | | | | | | | | | | | | Summary: This greatly simplifies our handling of SDNode::SubclassData. NFC, hopefully. :) See discussion in D23035 for discussion about the design API of these bitfields. Reviewers: chandlerc Subscribers: llvm-commits, rnk Differential Revision: https://reviews.llvm.org/D23036 llvm-svn: 279537
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-7/+7
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-2/+2
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* Use range algorithms instead of unpacking begin/endDavid Majnemer2016-08-111-2/+2
| | | | | | No functionality change is intended. llvm-svn: 278417
* Cleanup TransferDbgValuesNirav Dave2016-07-291-2/+9
| | | | | | | | | | | | | | | [DAG] Check debug values for invalidation before transferring and mark old debug values invalid when transferring to another SDValue. This fixes PR28613. Reviewers: jyknight, hans, dblaikie, echristo Subscribers: yaron.keren, ismail, llvm-commits Differential Revision: https://reviews.llvm.org/D22858 llvm-svn: 277135
* Fix DbgValue handling in SelectionDAG.Nirav Dave2016-07-281-2/+3
| | | | | | | [DAG] Relocate TransferDbgValues in ReplaceAllUsesWith(SDValue, SDValue) to before we modify the CSE maps. llvm-svn: 277027
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-21/+21
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-151-75/+57
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-151-9/+7
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* fix documentation comments; NFCSanjay Patel2016-07-111-42/+7
| | | | llvm-svn: 275101
* [DAG] make isConstantSplatVector() available to the rest of loweringSanjay Patel2016-07-101-0/+13
| | | | llvm-svn: 275025
* fix documentation comments; NFCSanjay Patel2016-07-101-11/+3
| | | | llvm-svn: 275021
* [CodeGen] Cleanup getVectorShuffle a bit to take advantage of its new ↵Craig Topper2016-07-011-16/+16
| | | | | | ArrayRef argument and its begin/end iterators. Also use 'int' type for number of elements and loop iterators to remove several typecasts. No functional change intended. llvm-svn: 274338
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a ↵Craig Topper2016-07-011-2/+4
| | | | | | | | pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array. llvm-svn: 274337
* [CodeGen] Make ShuffleVectorSDNode::commuteMask take a MutableArrayRef ↵Craig Topper2016-06-291-1/+1
| | | | | | instead of SmallVectorImpl. NFC. llvm-svn: 274095
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-231-7/+24
| | | | | | | | | | | | | | | | | | | | | Recommiting after correcting over-eager Debug Value transfer fixing PR28270. [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 273585
* Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as ↵Peter Collingbourne2016-06-231-18/+1
| | | | | | it caused pr28270. llvm-svn: 273518
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-221-1/+18
| | | | | | | | | | | | | | | | | | | | | Recommiting after fixing over-aggressive assertion [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 273456
* [SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCalleeKrzysztof Parzyszek2016-06-221-3/+3
| | | | | | | | | | | The setCallee function will set the number of fixed arguments based on the size of the argument list. The FixedArgs parameter was often explicitly set to 0, leading to a lack of consistent value for non- vararg functions. Differential Revision: http://reviews.llvm.org/D20376 llvm-svn: 273403
* Apply another batch of fixes from clang-tidy's ↵Benjamin Kramer2016-06-171-1/+1
| | | | | | | | performance-unnecessary-value-param. Contains some manual fixes. No functionality change intended. llvm-svn: 273047
* Revert "Preserve DebugInfo when replacing values in DAGCombiner"Nirav Dave2016-06-151-18/+1
| | | | | | | | | Reverting due to assertion failure in lib/CodeGen/SelectionDAG/InstrEmitter.cpp This reverts commit r272792. llvm-svn: 272799
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-151-1/+18
| | | | | | | | | | | | | | | | | | | [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 272792
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-254/+230
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* Avoid copies of std::strings and APInt/APFloats where we only read from itBenjamin Kramer2016-06-081-3/+3
| | | | | | | | As suggested by clang-tidy's performance-unnecessary-copy-initialization. This can easily hit lifetime issues, so I audited every change and ran the tests under asan, which came back clean. llvm-svn: 272126
* Simplify std::all_of predicate (to one line) by using llvm::all_of. NFCI.Simon Pilgrim2016-05-251-2/+1
| | | | llvm-svn: 270749
* [SelectionDAG] Add smarts for BSWAP in computeKnownBits.Chad Rosier2016-05-251-0/+6
| | | | llvm-svn: 270738
* [SelectionDAG] rename/move isKnownToBeAPowerOfTwo() from TargetLowering (NFC)Sanjay Patel2016-05-191-0/+29
| | | | | | | | | There are at least 2 places (DAGCombiner, X86ISelLowering) where this could be used instead of ad-hoc and watered down code that is trying to match a power-of-2 pattern. Differential Revision: http://reviews.llvm.org/D20439 llvm-svn: 270073
* SDAG: Have SelectNodeTo replace uses if it CSE's instead of morphing a nodeJustin Bogner2016-05-111-3/+7
| | | | | | | | It's awkward to force callers of SelectNodeTo to figure out whether the node was morphed or CSE'd. Update uses here instead of requiring callers to (sometimes) do it. llvm-svn: 269235
* [SelectionDAG] Added bitreverse(bitreverse(v)) --> vSimon Pilgrim2016-05-071-0/+6
| | | | | | Added bitreverse creation testing llvm-svn: 268865
* DebugInfo: Avoid propagating incorrect debug locations in SelectionDAG via CSE.Wolfgang Pieb2016-05-021-31/+37
| | | | | | | | | | | | | | | | | | Summary: When SelectionDAG performs CSE it is possible that the context's source location is different from that of the selected node. This can lead to incorrect line number records. We update the debug location to the one that occurs earlier in the instruction sequence. This fixes PR21006. Reviewers: echristo, sdmitrouk Subscribers: jevinskie, asl, llvm-commits Differential Revision: http://reviews.llvm.org/D12094 llvm-svn: 268323
* Fix grammar and correct comment - the debug information wasn't incorrect, ↵Eric Christopher2016-05-021-2/+2
| | | | | | rather suboptimal. llvm-svn: 268211
* Unify XDEBUG and EXPENSIVE_CHECKS (into the latter), and add an option to ↵Filipe Cabecinhas2016-04-291-2/+2
| | | | | | | | | | | | | | | | | | | the cmake build to enable them. Summary: Historically, we had a switch in the Makefiles for turning on "expensive checks". This has never been ported to the cmake build, but the (dead-ish) code is still around. This will also make it easier to turn it on in buildbots. Reviewers: chandlerc Subscribers: jyknight, mzolotukhin, RKSimon, gberry, llvm-commits Differential Revision: http://reviews.llvm.org/D19723 llvm-svn: 268050
* [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI.Ahmed Bougacha2016-04-261-26/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D17176 llvm-svn: 267606
* [PR27390] [CodeGen] Reject indexed loads in CombinerDAG.Marcin Koscielnicki2016-04-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | visitAND, when folding and (load) forgets to check which output of an indexed load is involved, happily folding the updated address output on the following testcase: target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" %typ = type { i32, i32 } define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) { %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1 %1 = load i32, i32* %b, align 4 %2 = ptrtoint i32* %b to i64 %3 = and i64 %2, -35184372088833 %4 = inttoptr i64 %3 to i32* %_msld = load i32, i32* %4, align 4 %zzz = add i32 %1, %_msld ret i32 %zzz } Fix this by checking ResNo. I've found a few more places that currently neglect to check for indexed load, and tightened them up as well, but I don't have test cases for them. In fact, they might not be triggerable at all, at least with current targets. Still, better safe than sorry. Differential Revision: http://reviews.llvm.org/D19202 llvm-svn: 267420
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [CodeGen] Remove constant-folding dead code. NFC.Ahmed Bougacha2016-04-121-12/+4
| | | | | | | | | | | This code was specific to vector operations with scalar operands: all the opcodes in FoldValue (via FoldConstantArithmetic) can't match those criteria. Replace it with an assert if that ever changes: at that point, we might need to add back a splat BUILD_VECTOR. llvm-svn: 266100
* [x86] use BMI 'andn' for logic + compare ops Sanjay Patel2016-04-091-0/+4
| | | | | | | | | | With BMI, we can use 'andn' to save an instruction when the result is only used in a compare. This is related to one of the potential sequences to check 'isfinite' in: https://llvm.org/bugs/show_bug.cgi?id=27164 Differential Revision: http://reviews.llvm.org/D18910 llvm-svn: 265875
* Fix Load Control Dependence in MemCpy GenerationNirav Dave2016-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Memcpy lowering we had missed a dependence from the load of the operation to successor operations. This causes us to potentially construct an in initial DAG with a memory dependence not fully represented in the chain sub-DAG but rather require looking at the entire DAG breaking alias analysis by allowing incorrect repositioning of memory operations. To work around this, r200033 changed DAGCombiner::GatherAllAliases to be conservative if any possible issues to happen. Unfortunately this check forbade many non-problematic situations as well. For example, it's common for incoming argument lowering to add a non-aliasing load hanging off of EntryNode. Then, if GatherAllAliases visited EntryNode, it would find that other (unvisited) use of the EntryNode chain, and just give up entirely. Furthermore, the check was incomplete: it would not actually detect all such potentially problematic DAG constructions, because GatherAllAliases did not guarantee to visit all chain nodes going up to the root EntryNode. This is in general fine -- giving up early will just miss a potential optimization, not generate incorrect results. But, for this non-chain dependency detection code, it's possible that you could have a load attached to a higher-up chain node than any which were visited. If that load aliases your store, but the only dependency is through the value operand of a non-aliasing store, it would've been missed by this code, and potentially reordered. With the dependence added, this check can be removed and Alias Analysis can be much more aggressive. This fixes code quality regression in the Consecutive Store Merge cleanup (D14834). Test Change: ppc64-align-long-double.ll now may see multiple serializations of its stores Differential Revision: http://reviews.llvm.org/D18062 llvm-svn: 265836
* Prevent X86ISelLowering from merging volatile loadsNirav Dave2016-03-311-6/+6
| | | | | | | | | | | | | Change isConsecutiveLoads to check that loads are non-volatile as this is a requirement for any load merges. Propagate change to two callers. Reviewers: RKSimon Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18546 llvm-svn: 265013
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