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* Replace APFloatBase static fltSemantics data members with getter functionsStephan Bergmann2016-12-141-4/+4
| | | | | | | | | | | | | At least the plugin used by the LibreOffice build (<https://wiki.documentfoundation.org/Development/Clang_plugins>) indirectly uses those members (through inline functions in LLVM/Clang include files in turn using them), but they are not exported by utils/extract_symbols.py on Windows, and accessing data across DLL/EXE boundaries on Windows is generally problematic. Differential Revision: https://reviews.llvm.org/D26671 llvm-svn: 289647
* [SelectionDAG] computeKnownBits - simplified knownbits sign extension. NFCI.Simon Pilgrim2016-12-131-13/+4
| | | | | | We don't need to extract+test the sign bit of the known ones/zeros, we can use sext which will handle all of this. llvm-svn: 289534
* [SelectionDAG] Add support for EXTRACT_SUBVECTOR to ComputeNumSignBitsSimon Pilgrim2016-12-121-0/+2
| | | | | | Pre-commit as discussed on D27657 llvm-svn: 289425
* [SelectionDAG] Add ability for computeKnownBits to peek through bitcasts ↵Simon Pilgrim2016-12-101-1/+23
| | | | | | | | from 'large element' scalar/vector to 'small element' vector. Extension to D27129 which already supported bitcasts from 'small element' vector to 'large element' scalar/vector types. llvm-svn: 289329
* [SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes (REAPPLIED)Simon Pilgrim2016-12-091-0/+36
| | | | | | Reapplied with fix for PR31323 - X86 SSE2 vXi16 multiplies for illegal types were creating CONCAT_VECTORS nodes with vector inputs that might not total the number of elements in the result type. llvm-svn: 289232
* [SelectionDAG] Use SelectionDAG.getBuildVector helper. NFCI.Simon Pilgrim2016-12-091-8/+5
| | | | | | Makes interception of BUILD_VECTOR creation easier for debugging. llvm-svn: 289218
* [SelectionDAG] Add additional checks to CONCAT_VECTORS creationSimon Pilgrim2016-12-091-0/+10
| | | | | | Part of the work for PR31323 - add extra asserts checking that the input vectors are of consistent type and result in the correct number of vector elements. llvm-svn: 289214
* [SelectionDAG] Add partial BITCAST support to computeKnownBitsSimon Pilgrim2016-12-091-0/+44
| | | | | | | | | | Adds support for bitcasting a little endian 'small element' vector to 'large element' scalar/vector (e.g. v16i8 to v4i32 or v2i32 to i64), which is required for PR30845. We extract the knownbits for each 'small element' part and concatenate the results together. We can add support for big endian and 'large element' scalar/vector to 'small element' vector bitcasting once we have test cases for them. Differential Revision: https://reviews.llvm.org/D27129 llvm-svn: 289200
* Revert "[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes"Daniel Jasper2016-12-091-36/+0
| | | | | | | | This reverts commit r288916 as it is currently causing a crasher in Halide. Reproducer on llvm.org/PR31323. While it might be that halide is generating invalid IR, llc shouldn't crash. llvm-svn: 289194
* [SelectionDAG] Add knownbits support for vector demandedelts in ↵Simon Pilgrim2016-12-071-2/+4
| | | | | | SMAX/SMIN/UMAX/UMIN opcodes llvm-svn: 288926
* [SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodesSimon Pilgrim2016-12-071-0/+36
| | | | llvm-svn: 288916
* [SelectionDAG] Removed old knownbits TODO comment. NFCI.Simon Pilgrim2016-12-071-3/+0
| | | | | | EXTRACT_VECTOR_ELT does support demanded elts if the element index is known and in range. llvm-svn: 288913
* [SelectionDAG] We can ignore knownbits from an undef shuffle vector index if ↵Simon Pilgrim2016-12-061-3/+3
| | | | | | we don't actually demand that element llvm-svn: 288839
* Avoid repeated calls to Op.getOpcode(). NFCI.Simon Pilgrim2016-12-061-3/+4
| | | | llvm-svn: 288814
* DAG: Fold out out of bounds insert_vector_eltMatt Arsenault2016-12-031-0/+7
| | | | | | | getNode already prevents formation of out of bounds constant extract_vector_elts. Do the same for insert_vector_elt. llvm-svn: 288603
* [DAGCombiner] Fix infinite loop in vector mul/shl combiningJohn Brawn2016-11-231-12/+9
| | | | | | | | | | | | | | | | | | | | | | We have the following DAGCombiner transformations: (mul (shl X, c1), c2) -> (mul X, c2 << c1) (mul (shl X, C), Y) -> (shl (mul X, Y), C) (shl (mul x, c1), c2) -> (mul x, c1 << c2) Usually the constant shift is optimised by SelectionDAG::getNode when it is constructed, by SelectionDAG::FoldConstantArithmetic, but when we're dealing with vectors and one of those vector constants contains an undef element FoldConstantArithmetic does not fold and we enter an infinite loop. Fix this by making FoldConstantArithmetic use getNode to decide how to fold each vector element, the same as FoldConstantVectorArithmetic does, and rather than adding the constant shift to the work list instead only apply the transformation if it's already been folded into a constant, as if it's not we're going to loop endlessly. Additionally add missing NoOpaques to one of those transformations, which I noticed when writing the tests for this. Differential Revision: https://reviews.llvm.org/D26605 llvm-svn: 287766
* [SelectionDAG] ComputeNumSignBits of TRUNCATE operationsSimon Pilgrim2016-11-221-3/+7
| | | | | | | | | | Add basic ComputeNumSignBits support for TRUNCATE ops for cases where the source's number of sign bits overlaps with the truncated size. Improves X86 SIGN_EXTEND_IN_REG vector cases which were needlessly sign extending boolean vector results. Differential Revision: https://reviews.llvm.org/D26851 llvm-svn: 287635
* [SelectionDAG] Add ComputeNumSignBits support for CONCAT_VECTORS opcodeSimon Pilgrim2016-11-211-0/+7
| | | | llvm-svn: 287541
* [SelectionDAG] Add knowbits support for CONCAT_VECTOR opcodeSimon Pilgrim2016-11-181-0/+18
| | | | llvm-svn: 287387
* [SelectionDAG] Add support for vector demandedelts in BSWAP opcodesSimon Pilgrim2016-11-111-1/+2
| | | | llvm-svn: 286582
* [SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodesSimon Pilgrim2016-11-111-6/+10
| | | | llvm-svn: 286578
* [SelectionDAG] Add support for vector demandedelts in UDIV opcodesSimon Pilgrim2016-11-111-2/+4
| | | | llvm-svn: 286576
* [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodesSimon Pilgrim2016-11-101-3/+6
| | | | llvm-svn: 286516
* [SelectionDAG] Add support for splatted vectors in SUB opcodeSimon Pilgrim2016-11-101-1/+1
| | | | llvm-svn: 286509
* [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodesSimon Pilgrim2016-11-101-1/+2
| | | | llvm-svn: 286481
* [SelectionDAG] Add support for vector demandedelts in MUL opcodesSimon Pilgrim2016-11-101-3/+5
| | | | llvm-svn: 286471
* [SelectionDAG] Add support for vector demandedelts in SRA opcodesSimon Pilgrim2016-11-101-1/+2
| | | | llvm-svn: 286461
* [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodesSimon Pilgrim2016-11-101-2/+4
| | | | llvm-svn: 286448
* [SelectionDAG] Add support for vector demandedelts in XOR opcodesSimon Pilgrim2016-11-061-2/+4
| | | | llvm-svn: 286075
* [SelectionDAG] Add support for vector demandedelts in OR opcodesSimon Pilgrim2016-11-061-2/+4
| | | | llvm-svn: 286071
* Use !operator to test if APInt is zero/non-zero. NFCI.Simon Pilgrim2016-11-021-3/+3
| | | | | | Avoids APInt construction and slower comparisons. llvm-svn: 285822
* [DAGCombiner] (REAPPLIED) Add vector demanded elements support to ↵Simon Pilgrim2016-10-291-13/+111
| | | | | | | | | | | | | | | | | | | | computeKnownBits Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander! Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285494
* [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has ↵Simon Pilgrim2016-10-281-0/+4
| | | | | | | | no known bits No need to check the remaining elements - no common known bits are available. llvm-svn: 285399
* [SelectionDAG] Tidyup UDIV computeKnownBits implementationSimon Pilgrim2016-10-281-2/+0
| | | | | | No need to clear KnownOne2/KnownZero2 bits as the next call to computeKnownBits will overwrite them anyway llvm-svn: 285398
* [SelectionDAG] Increment computeKnownBits recursion depth for ↵Simon Pilgrim2016-10-281-2/+2
| | | | | | SMIN/SMAX/UMIN/UMAX like all other ops llvm-svn: 285397
* Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits"Juergen Ributzka2016-10-281-111/+13
| | | | | | | This seems to have increased LTO compile time bejond 2x of previous builds. See http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto/10676/ llvm-svn: 285381
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsSimon Pilgrim2016-10-271-13/+111
| | | | | | | | | | | | | | | | Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285296
* [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar ↵Simon Pilgrim2016-10-241-6/+7
| | | | | | | | | | or vector splats Use isConstOrConstSplat helper. Also use APInt instead of getZExtValue directly to avoid out of range issues. llvm-svn: 285033
* Use SDValue::getConstantOperandVal() helper. NFCI.Simon Pilgrim2016-10-241-4/+2
| | | | llvm-svn: 285025
* CodeGen: Do not add a global's address space to the folding set profile.Peter Collingbourne2016-10-241-2/+0
| | | | | | | It is already part of the type (which is part of the global, which is already being added), so there's no need to do it. llvm-svn: 285002
* [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constantSanjay Patel2016-10-231-43/+32
| | | | llvm-svn: 284953
* [DAG] enhance computeKnownBits to handle SHL with vector splat constantSanjay Patel2016-10-211-10/+9
| | | | | | Also, use APInt to avoid crashing on types larger than vNi64. llvm-svn: 284874
* [DAG] use isConstOrConstSplat in ComputeNumSignBits to optimize SRASanjay Patel2016-10-171-1/+1
| | | | | | | | | | | | | | The scalar version of this pattern was noted in: https://reviews.llvm.org/D25485 and fixed with: https://reviews.llvm.org/rL284395 More refactoring of the constant/splat helpers is needed and will happen in follow-up patches. Differential Revision: https://reviews.llvm.org/D25685 llvm-svn: 284424
* [DAG] make isConstOrConstSplat and isConstOrConstSplatFP more accessible; NFCSanjay Patel2016-10-171-0/+34
| | | | | | | | | | | | As noted in: https://reviews.llvm.org/D25685 This is the next-to-smallest step needed to enable the ComputeNumSignBits fix in that patch. In a minor attempt to keep some structure, we're pulling the FP helper over along with its integer sibling, but clearly we can and should do more refactoring of the similar helper functions in DAGCombiner and SelectionDAG to simplify and not duplicate functionality. llvm-svn: 284421
* [SDAG] Use ABI type alignment for constant pools when optimizing for sizeJames Molloy2016-10-171-1/+3
| | | | | | | | SelectionDAG::getConstantPool will automatically determine an appropriate alignment if one is not specified. It does this by querying the type's preferred alignment. This can end up creating quite a lot of padding when the preferred alignment for vectors is 128. In optimize-for-size mode, it makes sense to instead query the ABI type alignment which is often smaller and causes less padding. llvm-svn: 284381
* [MachineMemOperand] Move synchronization scope and atomic orderings from ↵Konstantin Zhuravlyov2016-10-151-32/+15
| | | | | | | | SDNode to MachineMemOperand, and remove redundant getAtomic* member functions from SelectionDAG. Differential Revision: https://reviews.llvm.org/D24577 llvm-svn: 284312
* DAG: Setting Masked-Expand-Load as a variant of Masked-Load nodeElena Demikhovsky2016-10-091-6/+6
| | | | | | | | | | Masked-expand-load node represents load operation that loads a variable amount of elements from memory according to amount of "true" bits in the mask and expands the loaded elements according to their position in the mask vector. Right now, the node is used in intrinsics for VEXPAND* instructions. The work is done towards implementation of masked.expandload and masked.compressstore intrinsics. Differential Revision: https://reviews.llvm.org/D25322 llvm-svn: 283694
* Delete some dead code in SelectionDAG (NFC)Vedant Kumar2016-10-061-53/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D24435 llvm-svn: 283505
* [DAG] Teach computeKnownBits and ComputeNumSignBits in SelectionDAG to look ↵Bjorn Pettersson2016-10-051-0/+34
| | | | | | | | | | | | | | | | | through EXTRACT_VECTOR_ELT. Summary: Both computeKnownBits and ComputeNumSignBits can now do a simple look-through of EXTRACT_VECTOR_ELT. It will compute the result based on the known bits (or known sign bits) for the vector that the element is extracted from. Reviewers: bogner, tstellarAMD, mkuper Subscribers: wdng, RKSimon, jyknight, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D25007 llvm-svn: 283347
* [X86][avx512] Fix bug in masked compress store.Ayman Musa2016-09-261-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D23984 llvm-svn: 282381
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