| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
| |
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
llvm-svn: 100090
|
|
|
|
| |
llvm-svn: 99948
|
|
|
|
|
|
|
|
|
| |
memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
llvm-svn: 99928
|
|
|
|
| |
llvm-svn: 99901
|
|
|
|
| |
llvm-svn: 99836
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.
Here is a theoretical example that illustrates why the placement is important.
tmp1 =
store tmp1 -> x
...
tmp2 = add ...
...
call
...
store tmp2 -> x
Now mem2reg comes along:
tmp1 =
dbg_value (tmp1 -> x)
...
tmp2 = add ...
...
call
...
dbg_value (tmp2 -> x)
When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1.
Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers").
This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed.
llvm-svn: 99469
|
|
|
|
|
|
|
| |
RecyclingAllocator to allow client code to be simpler, and
simplify several clients.
llvm-svn: 98847
|
|
|
|
| |
llvm-svn: 98548
|
|
|
|
|
|
| |
not all unary nodes necessarily have a simple result type.
llvm-svn: 98547
|
|
|
|
| |
llvm-svn: 98513
|
|
|
|
| |
llvm-svn: 98501
|
|
|
|
|
|
|
|
| |
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
llvm-svn: 98463
|
|
|
|
|
|
|
| |
No functional effect yet. This is still evolving and should
not be viewed as final.
llvm-svn: 98195
|
|
|
|
| |
llvm-svn: 97914
|
|
|
|
| |
llvm-svn: 97735
|
|
|
|
|
|
|
|
|
|
| |
CSE and recursive RAUW calls delete a node from the use list,
invalidating the use list iterator. There's currently no known
way to reproduce this in an unmodified LLVM, however there's no
fundamental reason why a SelectionDAG couldn't be formed which
would trigger this case.
llvm-svn: 97665
|
|
|
|
| |
llvm-svn: 97536
|
|
|
|
|
|
| |
(the most general) the others are dead.
llvm-svn: 97511
|
|
|
|
| |
llvm-svn: 97441
|
|
|
|
|
|
| |
case of MorphNodeTo directly.
llvm-svn: 97417
|
|
|
|
| |
llvm-svn: 97072
|
|
|
|
|
|
| |
more elegant.
llvm-svn: 97059
|
|
|
|
| |
llvm-svn: 97057
|
|
|
|
| |
llvm-svn: 97056
|
|
|
|
|
|
|
|
|
|
|
| |
necessary to swap the operands to handle NaN and negative zero properly.
Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.
llvm-svn: 97025
|
|
|
|
| |
llvm-svn: 97019
|
|
|
|
|
|
| |
creating a new node then replacing uses.
llvm-svn: 97000
|
|
|
|
| |
llvm-svn: 96971
|
|
|
|
| |
llvm-svn: 96956
|
|
|
|
|
|
| |
CSE'd or otherwise combined with temporal MemSDNodes.
llvm-svn: 96505
|
|
|
|
|
|
|
| |
and T->isPointerTy(). Convert most instances of the first form to the second form.
Requested by Chris.
llvm-svn: 96344
|
|
|
|
| |
llvm-svn: 96295
|
|
|
|
| |
llvm-svn: 96240
|
|
|
|
| |
llvm-svn: 95711
|
|
|
|
|
|
|
|
|
| |
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
|
|
|
|
| |
llvm-svn: 95012
|
|
|
|
|
|
|
|
| |
type is the same as the element type of the vector. EXTRACT_VECTOR_ELT can
be used to extended the width of an integer type. This fixes a bug for
Generic/vector-casts.ll on a ppc750.
llvm-svn: 94990
|
|
|
|
| |
llvm-svn: 94805
|
|
|
|
|
|
|
| |
"visit*" method is called, take the newly created nodes, walk them in a DFS
fashion, and if they don't have an ordering set, then give it one.
llvm-svn: 94757
|
|
|
|
|
|
|
|
|
| |
the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also,
keep track of the SDNode ordering by default. Eventually, we would like to make
this ordering a way to break a "tie" in the scheduler. However, doing that now
breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux.
llvm-svn: 94308
|
|
|
|
|
|
|
| |
points. This will help us find future problems like the one
described in PR6019.
llvm-svn: 94019
|
|
|
|
| |
llvm-svn: 93960
|
|
|
|
|
|
| |
understanding CannotYTetSelect and other errors easier.
llvm-svn: 93901
|
|
|
|
|
|
|
|
|
|
|
| |
print/dumpWithDepth allows one to dump a DAG up to N levels deep.
dump/printWithFullDepth prints the whole DAG, subject to a depth limit
on 100 in the default case (to prevent infinite recursion).
Have CannotYetSelect to a dumpWithFullDepth so it is clearer exactly
what the non-matching DAG looks like.
llvm-svn: 93538
|
|
|
|
|
|
|
|
|
|
| |
really does need to be a vector type, because
TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type,
and it needs to be able to distinguish between vectors and scalars.
Also, fix some more issues with legalization of vector casts.
llvm-svn: 93043
|
|
|
|
|
|
|
|
|
|
| |
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))
Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
llvm-svn: 92849
|
|
|
|
| |
llvm-svn: 92569
|
|
|
|
|
|
|
|
| |
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
llvm-svn: 91880
|
|
|
|
|
|
| |
- Modify the "dump" method to emit the order of an SDNode.
llvm-svn: 91845
|
|
|
|
| |
llvm-svn: 91834
|