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* [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has ↵Simon Pilgrim2016-10-281-0/+4
| | | | | | | | no known bits No need to check the remaining elements - no common known bits are available. llvm-svn: 285399
* [SelectionDAG] Tidyup UDIV computeKnownBits implementationSimon Pilgrim2016-10-281-2/+0
| | | | | | No need to clear KnownOne2/KnownZero2 bits as the next call to computeKnownBits will overwrite them anyway llvm-svn: 285398
* [SelectionDAG] Increment computeKnownBits recursion depth for ↵Simon Pilgrim2016-10-281-2/+2
| | | | | | SMIN/SMAX/UMIN/UMAX like all other ops llvm-svn: 285397
* Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits"Juergen Ributzka2016-10-281-111/+13
| | | | | | | This seems to have increased LTO compile time bejond 2x of previous builds. See http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto/10676/ llvm-svn: 285381
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsSimon Pilgrim2016-10-271-13/+111
| | | | | | | | | | | | | | | | Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285296
* [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar ↵Simon Pilgrim2016-10-241-6/+7
| | | | | | | | | | or vector splats Use isConstOrConstSplat helper. Also use APInt instead of getZExtValue directly to avoid out of range issues. llvm-svn: 285033
* Use SDValue::getConstantOperandVal() helper. NFCI.Simon Pilgrim2016-10-241-4/+2
| | | | llvm-svn: 285025
* CodeGen: Do not add a global's address space to the folding set profile.Peter Collingbourne2016-10-241-2/+0
| | | | | | | It is already part of the type (which is part of the global, which is already being added), so there's no need to do it. llvm-svn: 285002
* [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constantSanjay Patel2016-10-231-43/+32
| | | | llvm-svn: 284953
* [DAG] enhance computeKnownBits to handle SHL with vector splat constantSanjay Patel2016-10-211-10/+9
| | | | | | Also, use APInt to avoid crashing on types larger than vNi64. llvm-svn: 284874
* [DAG] use isConstOrConstSplat in ComputeNumSignBits to optimize SRASanjay Patel2016-10-171-1/+1
| | | | | | | | | | | | | | The scalar version of this pattern was noted in: https://reviews.llvm.org/D25485 and fixed with: https://reviews.llvm.org/rL284395 More refactoring of the constant/splat helpers is needed and will happen in follow-up patches. Differential Revision: https://reviews.llvm.org/D25685 llvm-svn: 284424
* [DAG] make isConstOrConstSplat and isConstOrConstSplatFP more accessible; NFCSanjay Patel2016-10-171-0/+34
| | | | | | | | | | | | As noted in: https://reviews.llvm.org/D25685 This is the next-to-smallest step needed to enable the ComputeNumSignBits fix in that patch. In a minor attempt to keep some structure, we're pulling the FP helper over along with its integer sibling, but clearly we can and should do more refactoring of the similar helper functions in DAGCombiner and SelectionDAG to simplify and not duplicate functionality. llvm-svn: 284421
* [SDAG] Use ABI type alignment for constant pools when optimizing for sizeJames Molloy2016-10-171-1/+3
| | | | | | | | SelectionDAG::getConstantPool will automatically determine an appropriate alignment if one is not specified. It does this by querying the type's preferred alignment. This can end up creating quite a lot of padding when the preferred alignment for vectors is 128. In optimize-for-size mode, it makes sense to instead query the ABI type alignment which is often smaller and causes less padding. llvm-svn: 284381
* [MachineMemOperand] Move synchronization scope and atomic orderings from ↵Konstantin Zhuravlyov2016-10-151-32/+15
| | | | | | | | SDNode to MachineMemOperand, and remove redundant getAtomic* member functions from SelectionDAG. Differential Revision: https://reviews.llvm.org/D24577 llvm-svn: 284312
* DAG: Setting Masked-Expand-Load as a variant of Masked-Load nodeElena Demikhovsky2016-10-091-6/+6
| | | | | | | | | | Masked-expand-load node represents load operation that loads a variable amount of elements from memory according to amount of "true" bits in the mask and expands the loaded elements according to their position in the mask vector. Right now, the node is used in intrinsics for VEXPAND* instructions. The work is done towards implementation of masked.expandload and masked.compressstore intrinsics. Differential Revision: https://reviews.llvm.org/D25322 llvm-svn: 283694
* Delete some dead code in SelectionDAG (NFC)Vedant Kumar2016-10-061-53/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D24435 llvm-svn: 283505
* [DAG] Teach computeKnownBits and ComputeNumSignBits in SelectionDAG to look ↵Bjorn Pettersson2016-10-051-0/+34
| | | | | | | | | | | | | | | | | through EXTRACT_VECTOR_ELT. Summary: Both computeKnownBits and ComputeNumSignBits can now do a simple look-through of EXTRACT_VECTOR_ELT. It will compute the result based on the known bits (or known sign bits) for the vector that the element is extracted from. Reviewers: bogner, tstellarAMD, mkuper Subscribers: wdng, RKSimon, jyknight, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D25007 llvm-svn: 283347
* [X86][avx512] Fix bug in masked compress store.Ayman Musa2016-09-261-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D23984 llvm-svn: 282381
* [DAG] Fix incorrect alignment of ext load.Nirav Dave2016-09-221-1/+1
| | | | | | | | | | | | Correctly use alignment size from loaded size not output value size. Reviewers: jyknight, tstellarAMD, arsenm Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23356 llvm-svn: 282177
* [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 ↵Craig Topper2016-09-181-1/+2
| | | | | | | | rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision. Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future. llvm-svn: 281868
* [X86][SSE] Improve recognition of uitofp conversions that can be performed ↵Simon Pilgrim2016-09-181-4/+0
| | | | | | | | | | | | | | as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-3/+3
| | | | llvm-svn: 281495
* getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCISanjay Patel2016-09-141-11/+9
| | | | llvm-svn: 281493
* getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits() ; NFCISanjay Patel2016-09-141-7/+5
| | | | llvm-svn: 281490
* getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-18/+18
| | | | llvm-svn: 281489
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-111-2/+4
| | | | | | | | | | | | | | | | | | | Summary: An IR load can be invariant, dereferenceable, neither, or both. But currently, MI's notion of invariance is IR-invariant && IR-dereferenceable. This patch splits up the notions of invariance and dereferenceability at the MI level. It's NFC, so adds some probably-unnecessary "is-dereferenceable" checks, which we can remove later if desired. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23371 llvm-svn: 281151
* [SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and ↵Simon Pilgrim2016-09-081-0/+20
| | | | | | | | | | | | SimplifyDemandedBits Add the ability to computeKnownBits and SimplifyDemandedBits to extract the known zero/one bits from BUILD_VECTOR, returning the known bits that are shared by every vector element. This is an initial step towards determining the sign bits of a vector (PR29079). Differential Revision: https://reviews.llvm.org/D24253 llvm-svn: 280927
* [SelectionDAG] Simplify extract_subvector( insert_subvector ( Vec, In, Idx ↵Simon Pilgrim2016-09-061-0/+6
| | | | | | | | | | | | ), Idx ) -> In If we are extracting a subvector that has just been inserted then we should just use the original inserted subvector. This has come up in certain several x86 shuffle lowering cases where we are crossing 128-bit lanes. Differential Revision: https://reviews.llvm.org/D24254 llvm-svn: 280715
* Propagate TBAA info in SelectionDAG::getIndexedLoadKrzysztof Parzyszek2016-08-291-1/+2
| | | | | | Patch by Pranav Bhandarkar. llvm-svn: 279998
* [SelectionDAG] Use a union of bitfield structs for SDNode::SubclassData.Justin Lebar2016-08-231-43/+18
| | | | | | | | | | | | | | | | | | Summary: This greatly simplifies our handling of SDNode::SubclassData. NFC, hopefully. :) See discussion in D23035 for discussion about the design API of these bitfields. Reviewers: chandlerc Subscribers: llvm-commits, rnk Differential Revision: https://reviews.llvm.org/D23036 llvm-svn: 279537
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-7/+7
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-2/+2
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* Use range algorithms instead of unpacking begin/endDavid Majnemer2016-08-111-2/+2
| | | | | | No functionality change is intended. llvm-svn: 278417
* Cleanup TransferDbgValuesNirav Dave2016-07-291-2/+9
| | | | | | | | | | | | | | | [DAG] Check debug values for invalidation before transferring and mark old debug values invalid when transferring to another SDValue. This fixes PR28613. Reviewers: jyknight, hans, dblaikie, echristo Subscribers: yaron.keren, ismail, llvm-commits Differential Revision: https://reviews.llvm.org/D22858 llvm-svn: 277135
* Fix DbgValue handling in SelectionDAG.Nirav Dave2016-07-281-2/+3
| | | | | | | [DAG] Relocate TransferDbgValues in ReplaceAllUsesWith(SDValue, SDValue) to before we modify the CSE maps. llvm-svn: 277027
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-21/+21
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-151-75/+57
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-151-9/+7
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* fix documentation comments; NFCSanjay Patel2016-07-111-42/+7
| | | | llvm-svn: 275101
* [DAG] make isConstantSplatVector() available to the rest of loweringSanjay Patel2016-07-101-0/+13
| | | | llvm-svn: 275025
* fix documentation comments; NFCSanjay Patel2016-07-101-11/+3
| | | | llvm-svn: 275021
* [CodeGen] Cleanup getVectorShuffle a bit to take advantage of its new ↵Craig Topper2016-07-011-16/+16
| | | | | | ArrayRef argument and its begin/end iterators. Also use 'int' type for number of elements and loop iterators to remove several typecasts. No functional change intended. llvm-svn: 274338
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a ↵Craig Topper2016-07-011-2/+4
| | | | | | | | pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array. llvm-svn: 274337
* [CodeGen] Make ShuffleVectorSDNode::commuteMask take a MutableArrayRef ↵Craig Topper2016-06-291-1/+1
| | | | | | instead of SmallVectorImpl. NFC. llvm-svn: 274095
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-231-7/+24
| | | | | | | | | | | | | | | | | | | | | Recommiting after correcting over-eager Debug Value transfer fixing PR28270. [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 273585
* Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as ↵Peter Collingbourne2016-06-231-18/+1
| | | | | | it caused pr28270. llvm-svn: 273518
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-221-1/+18
| | | | | | | | | | | | | | | | | | | | | Recommiting after fixing over-aggressive assertion [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 273456
* [SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCalleeKrzysztof Parzyszek2016-06-221-3/+3
| | | | | | | | | | | The setCallee function will set the number of fixed arguments based on the size of the argument list. The FixedArgs parameter was often explicitly set to 0, leading to a lack of consistent value for non- vararg functions. Differential Revision: http://reviews.llvm.org/D20376 llvm-svn: 273403
* Apply another batch of fixes from clang-tidy's ↵Benjamin Kramer2016-06-171-1/+1
| | | | | | | | performance-unnecessary-value-param. Contains some manual fixes. No functionality change intended. llvm-svn: 273047
* Revert "Preserve DebugInfo when replacing values in DAGCombiner"Nirav Dave2016-06-151-18/+1
| | | | | | | | | Reverting due to assertion failure in lib/CodeGen/SelectionDAG/InstrEmitter.cpp This reverts commit r272792. llvm-svn: 272799
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