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* Improve EXTRACT_VECTOR_ELT patch based on comments from DuncanMon P Wang2010-02-011-6/+9
| | | | llvm-svn: 95012
* Fixed a couple of optimization with EXTRACT_VECTOR_ELT that assumes the resultMon P Wang2010-02-011-1/+1
| | | | | | | | type is the same as the element type of the vector. EXTRACT_VECTOR_ELT can be used to extended the width of an integer type. This fixes a bug for Generic/vector-casts.ll on a ppc750. llvm-svn: 94990
* Change the SREM case to match the logic in the IR version ComputeMaskedBits.Duncan Sands2010-01-291-8/+17
| | | | llvm-svn: 94805
* Assign the ordering of SDNodes in a much less intrusive fashion. After theBill Wendling2010-01-281-1/+1
| | | | | | | "visit*" method is called, take the newly created nodes, walk them in a DFS fashion, and if they don't have an ordering set, then give it one. llvm-svn: 94757
* Remove the '-disable-scheduling' flag and replace it with the 'source' option ofBill Wendling2010-01-231-8/+5
| | | | | | | | | the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also, keep track of the SDNode ordering by default. Eventually, we would like to make this ordering a way to break a "tie" in the scheduler. However, doing that now breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux. llvm-svn: 94308
* When XDEBUG is enabled, check for SelectionDAG cycles at some keyDavid Greene2010-01-201-1/+35
| | | | | | | points. This will help us find future problems like the one described in PR6019. llvm-svn: 94019
* Add some asserts to check SelectionDAG problems earlier.David Greene2010-01-201-0/+12
| | | | llvm-svn: 93960
* Add some new debugging APIs to print out "raw" SelectionDAGs to makeDavid Greene2010-01-191-28/+24
| | | | | | understanding CannotYTetSelect and other errors easier. llvm-svn: 93901
* Add some debug routines to SelectionDAG to dump full DAGs.David Greene2010-01-151-0/+43
| | | | | | | | | | | print/dumpWithDepth allows one to dump a DAG up to N levels deep. dump/printWithFullDepth prints the whole DAG, subject to a depth limit on 100 in the default case (to prevent infinite recursion). Have CannotYetSelect to a dumpWithFullDepth so it is clearer exactly what the non-matching DAG looks like. llvm-svn: 93538
* Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNodeDan Gohman2010-01-091-11/+28
| | | | | | | | | | really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
* Teach dag combine to fold the following transformation more aggressively:Evan Cheng2010-01-061-0/+2
| | | | | | | | | | (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. llvm-svn: 92849
* Change errs() to dbgs().David Greene2010-01-051-10/+11
| | | | llvm-svn: 92569
* Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling2009-12-221-3/+3
| | | | | | | | return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. llvm-svn: 91880
* - Add a bit more plumbing assigning an order to SDNodes.Bill Wendling2009-12-211-1/+17
| | | | | | - Modify the "dump" method to emit the order of an SDNode. llvm-svn: 91845
* Place SDNodeOrdering.h in the directory it's used.Bill Wendling2009-12-211-1/+2
| | | | llvm-svn: 91834
* Use 4-arg getVTList) variant instead of generic one, when possibleAnton Korobeynikov2009-12-191-0/+1
| | | | llvm-svn: 91744
* Changes from review:Bill Wendling2009-12-181-133/+54
| | | | | | | | | | | - Move DisableScheduling flag into TargetOption.h - Move SDNodeOrdering into its own header file. Give it a minimal interface that doesn't conflate construction with storage. - Move assigning the ordering into the SelectionDAGBuilder. This isn't used yet, so there should be no functional changes. llvm-svn: 91727
* Reapply r91392, it was only unmasking the bug, and since TOT is still broken ↵Daniel Dunbar2009-12-161-29/+146
| | | | | | having it reverted does no good. llvm-svn: 91560
* Revert "Initial work on disabling the scheduler. This is a work in progress, andDaniel Dunbar2009-12-161-146/+29
| | | | | | | this", this broke llvm-gcc bootstrap for release builds on x86_64-apple-darwin10. llvm-svn: 91533
* Initial work on disabling the scheduler. This is a work in progress, and thisBill Wendling2009-12-151-29/+146
| | | | | | | | | | | | | | | stuff isn't used just yet. We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2' flags. The hypothesis is that the people who use these flags know what they are doing, and have hand-optimized the C code to reduce latencies and other conflicts. The idea behind our scheme to turn off scheduling is to create a map "on the side" during DAG generation. It will order the nodes by how they appeared in the code. This map is then used during scheduling to get the ordering. llvm-svn: 91392
* Fix integer cast code to handle vector types.Dan Gohman2009-12-141-19/+44
| | | | llvm-svn: 91362
* Fix weird typo which leads to unallocated memory access for nodes with 4 ↵Anton Korobeynikov2009-12-131-1/+1
| | | | | | results. llvm-svn: 91233
* Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman2009-12-111-11/+21
| | | | llvm-svn: 91158
* Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng2009-12-091-0/+6
| | | | | | isl lowering code. llvm-svn: 90925
* Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's ↵Evan Cheng2009-12-091-0/+43
| | | | | | primary used by selectdag passes. llvm-svn: 90922
* Infer alignment for non-fixed stack object.Evan Cheng2009-12-091-3/+4
| | | | llvm-svn: 90919
* Add const qualifier.Evan Cheng2009-12-091-1/+1
| | | | llvm-svn: 90918
* Refactor InferAlignment out of DAGCombine.Evan Cheng2009-12-091-0/+44
| | | | llvm-svn: 90917
* Added support to allow clients to custom widen. For X86, custom widen ↵Mon P Wang2009-11-301-0/+61
| | | | | | | | | vectors for divide/remainder since these operations can trap by unroll them and adding undefs for the resulting vector. llvm-svn: 90108
* Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman2009-11-231-18/+0
| | | | | | | | Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. llvm-svn: 89711
* We are not using DBG_STOPPOINT anymore.Devang Patel2009-11-211-19/+1
| | | | llvm-svn: 89536
* Target-independent support for TargetFlags on BlockAddress operands,Dan Gohman2009-11-201-5/+10
| | | | | | and support for blockaddresses in x86-32 PIC mode. llvm-svn: 89506
* Adjust isConstantSplat to allow for big-endian targets.Dale Johannesen2009-11-131-4/+7
| | | | | | PPC is such a target; make it work. llvm-svn: 87060
* Add a bool flag to StackObjects telling whether they reference spillDavid Greene2009-11-121-2/+2
| | | | | | | | | | | | | slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. llvm-svn: 87022
* Fix memoizing of CvtRndSatSDNodeMon P Wang2009-11-071-1/+2
| | | | llvm-svn: 86340
* Avoid printing a redundant space in SDNode->dump().Dan Gohman2009-11-051-2/+1
| | | | llvm-svn: 86151
* Make -print-machineinstrs more readable.Dan Gohman2009-10-311-2/+2
| | | | | | | | | | | | | | - Be consistent when referring to MachineBasicBlocks: BB#0. - Be consistent when referring to virtual registers: %reg1024. - Be consistent when referring to unknown physical registers: %physreg10. - Be consistent when referring to known physical registers: %RAX - Be consistent when referring to register 0: %reg0 - Be consistent when printing alignments: align=16 - Print jump table contents. - Don't print host addresses, in general. - and various other cleanups. llvm-svn: 85682
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+31
| | | | llvm-svn: 85556
* Remove some unnecessary spaces in debug output.Dan Gohman2009-10-291-3/+3
| | | | llvm-svn: 85536
* Rewrite SelectionDAG::isPredecessorOf to be iterative instead ofDan Gohman2009-10-281-21/+16
| | | | | | | recursive to avoid consuming extraordinary amounts of stack space when processing tall graphs. llvm-svn: 85369
* Fix null pointer dereference.Anton Korobeynikov2009-10-221-1/+1
| | | | llvm-svn: 84806
* -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng2009-10-181-41/+15
| | | | | | | | | | | stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. llvm-svn: 84424
* Only fixed stack objects and spill slots should be get FixedStack ↵Evan Cheng2009-10-181-15/+41
| | | | | | PseudoSourceValue. llvm-svn: 84411
* Revert 84315 for now. Re-thinking the patch.Evan Cheng2009-10-171-5/+5
| | | | llvm-svn: 84321
* Rename getFixedStack to getStackObject. The stack objects represented are notEvan Cheng2009-10-171-5/+5
| | | | | | necessarily fixed. Only those will negative frame indices are "fixed." llvm-svn: 84315
* Report errors correctly for unselected target intrinsics.Jakob Stoklund Olesen2009-10-151-6/+9
| | | | llvm-svn: 84193
* Introduce new convenience methods for sign extending orDuncan Sands2009-10-131-0/+12
| | | | | | | | | | | | truncating an SDValue (depending on whether the target type is bigger or smaller than the value's type); or zero extending or truncating it. Use it in a few places (this seems to be a popular operation, but I only modified cases of it in SelectionDAGBuild). In particular, the eh_selector lowering was doing this wrong due to a repeated rather than inverted test, fixed with this change. llvm-svn: 84027
* Make getMachineNode return a MachineSDNode* instead of a generic SDNode*Dan Gohman2009-10-101-42/+53
| | | | | | | since it won't do any folding. This will help avoid some inconvenient casting. llvm-svn: 83698
* Add a SelectionDAG getTargetInsertSubreg convenience function,Bob Wilson2009-10-081-0/+11
| | | | | | similar to getTargetExtractSubreg. llvm-svn: 83564
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-204/+309
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
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