summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-4/+3
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* EmitDbgValue doesn't need its EdgeMapping argument.Dan Gohman2010-04-301-7/+6
| | | | llvm-svn: 102742
* Add DBG_VALUE handling for byval parameters; thisDale Johannesen2010-04-261-3/+14
| | | | | | | produces a comment on targets that support it, but the Dwarf writer is not hooked up yet. llvm-svn: 102372
* - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo ↵Evan Cheng2010-04-261-12/+17
| | | | | | | | and rename it to emitFrameIndexDebugValue. - Teach spiller to modify DBG_VALUE instructions to reference spill slots. llvm-svn: 102323
* Fix -Wcast-qual warnings.Dan Gohman2010-04-171-2/+2
| | | | llvm-svn: 101655
* Scheduler assumes SDDbgValue nodes are in source order. That's true ↵Evan Cheng2010-03-251-0/+8
| | | | | | currently. But add an assertion to verify it. llvm-svn: 99501
* Remove a fixme that doesn't make sense any more.Evan Cheng2010-03-251-2/+0
| | | | llvm-svn: 99489
* Change how dbg_value sdnodes are converted into machine instructions. Their ↵Evan Cheng2010-03-251-16/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers. Here is a theoretical example that illustrates why the placement is important. tmp1 = store tmp1 -> x ... tmp2 = add ... ... call ... store tmp2 -> x Now mem2reg comes along: tmp1 = dbg_value (tmp1 -> x) ... tmp2 = add ... ... call ... dbg_value (tmp2 -> x) When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1. Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers"). This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed. llvm-svn: 99469
* Rename SDDbgValue.h to SDNodeDbgValue.h for consistency.Evan Cheng2010-03-141-1/+1
| | | | llvm-svn: 98513
* Progress towards shepherding debug info through SelectionDAG.Dale Johannesen2010-03-101-0/+19
| | | | | | | No functional effect yet. This is still evolving and should not be viewed as final. llvm-svn: 98195
* Change the scheduler from adding nodes in allnodes orderChris Lattner2010-02-241-2/+14
| | | | | | | | | | | | | | | | | | to adding them in a determinstic order (bottom up from the root) based on the structure of the graph itself. This updates tests for some random changes, interesting bits: CodeGen/Blackfin/promote-logic.ll no longer crashes. I have no idea why, but that's good right? CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but now compiles to have one fewer constant pool entry, making the expected load that was being folded disappear. Since it is an unreduced mass of gnast, I just removed it. This fixes PR6370 llvm-svn: 97023
* Enable pre-regalloc scheduling load clustering by default.Evan Cheng2010-01-221-7/+1
| | | | llvm-svn: 94255
* Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may ↵Evan Cheng2010-01-221-0/+130
| | | | | | improve cache locality. This is controlled by -cluster-loads for now. llvm-svn: 94148
* Change errs() to dbgs().David Greene2010-01-051-4/+4
| | | | llvm-svn: 92581
* Changes from review:Bill Wendling2009-12-181-6/+0
| | | | | | | | | | | - Move DisableScheduling flag into TargetOption.h - Move SDNodeOrdering into its own header file. Give it a minimal interface that doesn't conflate construction with storage. - Move assigning the ordering into the SelectionDAGBuilder. This isn't used yet, so there should be no functional changes. llvm-svn: 91727
* Reapply r91392, it was only unmasking the bug, and since TOT is still broken ↵Daniel Dunbar2009-12-161-0/+6
| | | | | | having it reverted does no good. llvm-svn: 91560
* Revert "Initial work on disabling the scheduler. This is a work in progress, andDaniel Dunbar2009-12-161-6/+0
| | | | | | | this", this broke llvm-gcc bootstrap for release builds on x86_64-apple-darwin10. llvm-svn: 91533
* Initial work on disabling the scheduler. This is a work in progress, and thisBill Wendling2009-12-151-0/+6
| | | | | | | | | | | | | | | stuff isn't used just yet. We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2' flags. The hypothesis is that the people who use these flags know what they are doing, and have hand-optimized the C code to reduce latencies and other conflicts. The idea behind our scheme to turn off scheduling is to create a map "on the side" during DAG generation. It will order the nodes by how they appeared in the code. This map is then used during scheduling to get the ordering. llvm-svn: 91392
* Create a new InstrEmitter class for translating SelectionDAG nodesDan Gohman2009-10-101-26/+42
| | | | | | | | into MachineInstrs. This is mostly just moving the code from ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr emitting from scheduling. llvm-svn: 83699
* The ScheduleDAG framework now requires an AliasAnalysis argument, thoughDan Gohman2009-10-091-1/+1
| | | | | | it isn't needed in the ScheduleDAGSDNodes schedulers. llvm-svn: 83691
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-13/+3
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Remove some not-really-used variables, as warnedDuncan Sands2009-09-061-2/+0
| | | | | | about by icc (#593, partial). Patch by Erick Tryzelaar. llvm-svn: 81115
* Use the schedule itinerary operand use/def cycle information to adjust ↵David Goodwin2009-08-191-4/+9
| | | | | | dependence edge latency for post-RA scheduling. llvm-svn: 79425
* Add callback to allow target to adjust latency of schedule dependency edge.David Goodwin2009-08-131-2/+10
| | | | llvm-svn: 78910
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-8/+8
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-9/+9
| | | | | | own struct type. llvm-svn: 78610
* Move more to raw_ostream, provide support for writing MachineBasicBlock,Daniel Dunbar2009-07-241-4/+4
| | | | | | LiveInterval, etc to raw_ostream. llvm-svn: 76965
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-021-7/+0
| | | | llvm-svn: 72712
* Make the implicit inputs and outputs of target-independentDale Johannesen2009-06-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. llvm-svn: 72707
* Don't set SUnit::hasPhysRegDefs to true unless the defs areDan Gohman2009-03-231-1/+4
| | | | | | actually have uses, which reflects the way it's used. llvm-svn: 67540
* Add a new bit to SUnit to record whether a node has implicit physregDan Gohman2009-03-231-3/+6
| | | | | | defs, regardless of whether they are actually used. llvm-svn: 67528
* Simplify this code; use a while instead of an if and a do-while.Dan Gohman2009-03-201-9/+6
| | | | llvm-svn: 67400
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-0/+8
| | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. llvm-svn: 64288
* Move ScheduleDAGSDNodes.h to be a private header. Front-endsDan Gohman2009-02-061-1/+1
| | | | | | | that previously included this header should include SchedulerRegistry.h instead. llvm-svn: 63937
* CreateVirtualRegisters does trivial copy coalescing. If a node def is used ↵Evan Cheng2009-01-161-0/+1
| | | | | | by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. llvm-svn: 62356
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-3/+2
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical ↵Evan Cheng2009-01-121-8/+22
| | | | | | | | register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet. llvm-svn: 62074
* CheckForPhysRegDependency should not return copy cost. It's not used. No ↵Evan Cheng2009-01-111-9/+4
| | | | | | functionality change. llvm-svn: 62036
* Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman2008-12-231-4/+14
| | | | | | code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions. llvm-svn: 61376
* Avoid an unnecessary call to allnodes_size(), which is linear.Dan Gohman2008-12-231-8/+11
| | | | llvm-svn: 61372
* Double the amount of memory reserved for SUnits. This is aDan Gohman2008-12-171-1/+3
| | | | | | | | | temporary workaround for an obscure bug. When node cloning is used, it is possible that more SUnits will be created, and if the SUnits std::vector has to reallocate, it will invalidate all the graph edges. llvm-svn: 61122
* Remove some special-case logic in ScheduleDAGSDNodes's Dan Gohman2008-12-161-10/+0
| | | | | | | latency computation code that is no longer needed with the new method for handling latencies. llvm-svn: 61074
* Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman2008-12-161-1/+7
| | | | | | | | | | | | | | computation code. Also, avoid adding output-depenency edges when both defs are dead, which frequently happens with EFLAGS defs. Compute Depth and Height lazily, and always in terms of edge latency values. For the schedulers that don't care about latency, edge latencies are set to 1. Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array. These are all subsumed by the Depth and Height fields. llvm-svn: 61073
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-091-1/+4
| | | | | | | | | | | | | | | | | The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. llvm-svn: 60806
* Use ComputeLatency in the MachineInstr scheduler.Dan Gohman2008-11-211-0/+1
| | | | llvm-svn: 59777
* Implement ComputeLatency for MachineInstr ScheduleDAGs. FactorDan Gohman2008-11-211-7/+9
| | | | | | | | some of the latency computation logic out of the SDNode ScheduleDAG code into a TargetInstrItineraries helper method to help with this. llvm-svn: 59761
* Experimental post-pass scheduling support. Post-pass schedulingDan Gohman2008-11-191-0/+257
is currently off by default, and can be enabled with -disable-post-RA-scheduler=false. This doesn't have a significant impact on most code yet because it doesn't yet do anything to address anti-dependencies and it doesn't attempt to disambiguate memory references. Also, several popular targets don't have pipeline descriptions yet. The majority of the changes here are splitting the SelectionDAG-specific code out of ScheduleDAG, so that ScheduleDAG can be moved to libLLVMCodeGen.a. The interface between ScheduleDAG-using code and the rest of the scheduling code is somewhat rough and will evolve. llvm-svn: 59676
OpenPOWER on IntegriCloud