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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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* Refactor / clean up code; remove td list scheduler special tie breaker (no ↵Evan Cheng2008-03-011-78/+59
| | | | | | real benefit). llvm-svn: 47779
* Update gcc 4.3 warnings fix patch with recent head changesAnton Korobeynikov2008-02-201-6/+13
| | | | llvm-svn: 47368
* Revert 47177, which was incorrect.Dan Gohman2008-02-161-1/+1
| | | | llvm-svn: 47196
* Skip over the defs and start at the uses when looking for operandsDan Gohman2008-02-151-1/+1
| | | | | | with the TIED_TO attribute. llvm-svn: 47177
* Use the TargetInstrDescr to determine the number of operandsDan Gohman2008-02-151-3/+3
| | | | | | | that should be checked for the TIED_TO attribute instead of using CountOperands. llvm-svn: 47176
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-15/+15
| | | | llvm-svn: 46930
* Use empty() instead of comparing size() with zero.Dan Gohman2008-01-291-1/+1
| | | | llvm-svn: 46514
* Fix a typo in a comment.Dan Gohman2008-01-291-1/+1
| | | | llvm-svn: 46513
* Fix a typo in a comment.Dan Gohman2008-01-291-1/+0
| | | | llvm-svn: 46508
* Special copy SUnit's do not have SDNode's.Evan Cheng2008-01-091-2/+2
| | | | llvm-svn: 45787
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-6/+6
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* simplify some code.Chris Lattner2008-01-071-10/+13
| | | | llvm-svn: 45693
* Rename all the M_* flags to be namespace qualified enums, and switch Chris Lattner2008-01-071-1/+1
| | | | | | | | all clients over to using predicates instead of these flags directly. These are now private values which are only to be used to statically initialize the tables. llvm-svn: 45692
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-9/+10
| | | | llvm-svn: 45680
* Update CodeGen for MRegisterInfo --> TargetInstrInfo changes.Owen Anderson2008-01-071-1/+1
| | | | llvm-svn: 45673
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-1/+0
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* More accurate checks for two-address constraints.Evan Cheng2007-12-201-8/+40
| | | | llvm-svn: 45259
* Bring back a burr scheduling heuristic that's still needed.Evan Cheng2007-12-201-5/+34
| | | | llvm-svn: 45252
* FIX for PR1799: When a load is unfolded from an instruction, check if it is ↵Evan Cheng2007-12-181-26/+36
| | | | | | a new node. If not, do not create a new SUnit. llvm-svn: 45157
* Bug fix. Passive nodes are not in SUnitMap.Evan Cheng2007-11-091-3/+6
| | | | llvm-svn: 43922
* Add pseudo dependency to force two-address instruction to be scheduled afterEvan Cheng2007-11-061-2/+5
| | | | | | | other uses. There was a overly restricted check that prevented some obvious cases. llvm-svn: 43762
* One mundane change: Change ReplaceAllUsesOfValueWith to *optionally* Chris Lattner2007-10-151-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | take a deleted nodes vector, instead of requiring it. One more significant change: Implement the start of a legalizer that just works on types. This legalizer is designed to run before the operation legalizer and ensure just that the input dag is transformed into an output dag whose operand and result types are all legal, even if the operations on those types are not. This design/impl has the following advantages: 1. When finished, this will *significantly* reduce the amount of code in LegalizeDAG.cpp. It will remove all the code related to promotion and expansion as well as splitting and scalarizing vectors. 2. The new code is very simple, idiomatic, and modular: unlike LegalizeDAG.cpp, it has no 3000 line long functions. :) 3. The implementation is completely iterative instead of recursive, good for hacking on large dags without blowing out your stack. 4. The implementation updates nodes in place when possible instead of deallocating and reallocating the entire graph that points to some mutated node. 5. The code nicely separates out handling of operations with invalid results from operations with invalid operands, making some cases simpler and easier to understand. 6. The new -debug-only=legalize-types option is very very handy :), allowing you to easily understand what legalize types is doing. This is not yet done. Until the ifdef added to SelectionDAGISel.cpp is enabled, this does nothing. However, this code is sufficient to legalize all of the code in 186.crafty, olden and freebench on an x86 machine. The biggest issues are: 1. Vectors aren't implemented at all yet 2. SoftFP is a mess, I need to talk to Evan about it. 3. No lowering to libcalls is implemented yet. 4. Various operations are missing etc. 5. There are FIXME's for stuff I hax0r'd out, like softfp. Hey, at least it is a step in the right direction :). If you'd like to help, just enable the #ifdef in SelectionDAGISel.cpp and compile code with it. If this explodes it will tell you what needs to be implemented. Help is certainly appreciated. Once this goes in, we can do three things: 1. Add a new pass of dag combine between the "type legalizer" and "operation legalizer" passes. This will let us catch some long-standing isel issues that we miss because operation legalization often obfuscates the dag with target-specific nodes. 2. We can rip out all of the type legalization code from LegalizeDAG.cpp, making it much smaller and simpler. When that happens we can then reimplement the core functionality left in it in a much more efficient and non-recursive way. 3. Once the whole legalizer is non-recursive, we can implement whole-function selectiondags maybe... llvm-svn: 42981
* EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG likeEvan Cheng2007-10-121-0/+13
| | | | | | | | | (almost) a register copy. However, it always coalesced to the register of the RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub- register uses which adds subtle complications to load folding, spiller rewrite, etc. llvm-svn: 42899
* Fix a typo in a comment.Dan Gohman2007-10-051-1/+1
| | | | llvm-svn: 42635
* Chain producing nodes cannot be moved, not chain reading nodes.Evan Cheng2007-10-051-5/+7
| | | | llvm-svn: 42627
* Oops. Didn't mean to leave this in.Evan Cheng2007-10-051-1/+0
| | | | llvm-svn: 42626
* If a node that defines a physical register that is expensive to copy. TheEvan Cheng2007-10-051-19/+132
| | | | | | | | | scheduler will try a number of tricks in order to avoid generating the copies. This may not be possible in case the node produces a chain value that prevent movement. Try unfolding the load from the node before to allow it to be moved / cloned. llvm-svn: 42625
* If two instructions are both two-address code, favors (schedule closer toEvan Cheng2007-09-281-3/+20
| | | | | | | terminator) the one that has a CopyToReg use. This fixes 2006-05-11-InstrSched.ll with -new-cc-modeling-scheme. llvm-svn: 42453
* Remove a poor scheduling heuristic.Evan Cheng2007-09-281-34/+5
| | | | llvm-svn: 42443
* Trim some unneeded fields.Evan Cheng2007-09-281-17/+8
| | | | llvm-svn: 42442
* Avoid inserting a live register more than once.Evan Cheng2007-09-271-8/+18
| | | | llvm-svn: 42410
* Boogs.Evan Cheng2007-09-271-10/+10
| | | | llvm-svn: 42388
* Be smarter about which node to force schedule. Reduce # of duplications + ↵Evan Cheng2007-09-271-84/+120
| | | | | | copies; Added statistics. llvm-svn: 42387
* Backtracking only when it won't create a cycle.Evan Cheng2007-09-271-23/+35
| | | | llvm-svn: 42384
* - Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo.Evan Cheng2007-09-261-65/+145
| | | | | | | - Added ability to emit cross class register copies to the BBRU scheduler. - More aggressive backtracking. llvm-svn: 42375
* Added major new capabilities to scheduler (only BURR for now) to support ↵Evan Cheng2007-09-251-71/+398
| | | | | | physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered. llvm-svn: 42284
* Use struct SDep instead of std::pair for SUnit pred and succ lists. First stepEvan Cheng2007-09-191-22/+22
| | | | | | in tracking physical register output dependencies. llvm-svn: 42125
* Bug fixes.Evan Cheng2007-09-131-4/+4
| | | | llvm-svn: 41900
* Minor cleanups to reduce some spurious differences between differentDan Gohman2007-08-201-9/+11
| | | | | | scheduler implementations. llvm-svn: 41191
* Skeleton of post-RA scheduler; doesn't do anything yet.Dale Johannesen2007-07-131-1/+1
| | | | | | | Change name of -sched option and DEBUG_TYPE to pre-RA-sched; adjust testcases. llvm-svn: 39816
* Remove unused variables.David Greene2007-06-291-3/+0
| | | | llvm-svn: 37816
* Remove unnecessary attributions in comments.David Greene2007-06-291-1/+1
| | | | llvm-svn: 37799
* Remove the "special tie breaker" because it resulted in inconsistentDavid Greene2007-06-291-10/+12
| | | | | | | ordering and thus violated the strict weak ordering requirement of priority_queue. Uncovered by _GLIBCXX_DEBUG. llvm-svn: 37794
* std::set is really really terrible. Switch to SmallPtrSet to reduce compile ↵Evan Cheng2007-06-221-4/+4
| | | | | | time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec. llvm-svn: 37701
* Fix a typo in a comment.Dan Gohman2007-04-261-1/+1
| | | | llvm-svn: 36485
* Estimate a cost using the possible number of scratch registers required and useEvan Cheng2007-03-141-9/+47
| | | | | | | | | | it as a late BURR scheduling tie-breaker. Intuitively, it's good to push down instructions whose results are liveout so their long live ranges won't conflict with other values which are needed inside the BB. Further prioritize liveout instructions by the number of operands which are calculated within the BB. llvm-svn: 35109
* Try schedule def + use closer whne Sethi-Ullman numbers are the same.Evan Cheng2007-03-131-6/+38
| | | | | | | | | | | | | | | | | | | | | e.g. t1 = op t2, c1 t3 = op t4, c2 and the following instructions are both ready. t2 = op c3 t4 = op c4 Then schedule t2 = op first. i.e. t4 = op c4 t2 = op c3 t1 = op t2, c1 t3 = op t4, c2 This creates more short live intervals which work better with the register allocator. llvm-svn: 35089
* switch the sched unit map over to use a DenseMap instead of std::map. ThisChris Lattner2007-02-031-5/+5
| | | | | | speeds up isel as a whole time by 2.6%. llvm-svn: 33810
* Fit in 80 columnsChris Lattner2007-02-011-5/+7
| | | | llvm-svn: 33745
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