| Commit message (Collapse) | Author | Age | Files | Lines |
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instructions
to be emitted.
Don't add one to the latency of a completed instruction if the latency of the
op is 0.
llvm-svn: 26718
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predecessor to finish before they can start.
llvm-svn: 26717
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operands have all issued, but whose results are not yet available. This
allows us to compile:
int G;
int test(int A, int B, int* P) {
return (G+A)*(B+1);
}
to:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
addi r4, r4, 1
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
instead of this, which has a stall between the lis/lwz:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
addi r4, r4, 1
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
llvm-svn: 26716
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which cycle it lands on.
llvm-svn: 26714
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llvm-svn: 26713
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is together, and direction independent code is together.
llvm-svn: 26712
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merge succs/chainsuccs -> succs set
This has no functionality change, simplifies the code, and reduces the size
of sunits.
llvm-svn: 26711
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llvm-svn: 26690
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llvm-svn: 26687
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llvm-svn: 26686
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llvm-svn: 26684
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llvm-svn: 26683
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llvm-svn: 26682
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keep track of a sense of "mobility", i.e. how many other nodes scheduling one
node will free up. For something like this:
float testadd(float *X, float *Y, float *Z, float *W, float *V) {
return (*X+*Y)*(*Z+*W)+*V;
}
For example, this makes us schedule *X then *Y, not *X then *Z. The former
allows us to issue the add, the later only lets us issue other loads.
This turns the above code from this:
_testadd:
lfs f0, 0(r3)
lfs f1, 0(r6)
lfs f2, 0(r4)
lfs f3, 0(r5)
fadds f0, f0, f2
fadds f1, f3, f1
lfs f2, 0(r7)
fmadds f1, f0, f1, f2
blr
into this:
_testadd:
lfs f0, 0(r6)
lfs f1, 0(r5)
fadds f0, f1, f0
lfs f1, 0(r4)
lfs f2, 0(r3)
fadds f1, f2, f1
lfs f2, 0(r7)
fmadds f1, f1, f0, f2
blr
llvm-svn: 26680
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priority impls that want to be notified when a node is scheduled
llvm-svn: 26678
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llvm-svn: 26676
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llvm-svn: 26646
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llvm-svn: 26637
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latency priority function.
llvm-svn: 26636
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Only enable this with -use-sched-latencies, I'll enable it by default with a
clean nightly tester run tonight.
PPC is the only target that provides latency info currently.
llvm-svn: 26634
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llvm-svn: 26632
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llvm-svn: 26631
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class, sever its implementation from the interface. Now we can provide new
implementations of the same interface (priority computation) without touching
the scheduler itself.
llvm-svn: 26630
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of the ScheduleDAGList class into a new SchedulingPriorityQueue class.
llvm-svn: 26613
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llvm-svn: 26612
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llvm-svn: 26611
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llvm-svn: 26609
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llvm-svn: 26608
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things like copyfromreg.
llvm-svn: 26586
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llvm-svn: 26573
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llvm-svn: 26572
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range to be generated.
llvm-svn: 26570
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targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
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llvm-svn: 26567
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noops as null pointers in the instruction sequence.
llvm-svn: 26564
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copyfromreg nodes. Clearly useful!
llvm-svn: 26559
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llvm-svn: 26558
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function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
llvm-svn: 26552
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bounds its lifetime.
llvm-svn: 26550
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llvm-svn: 26500
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llvm-svn: 26498
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a predecessor appearing more than once in the operand list was counted as
multiple predecessor; priority1 should be updated during scheduling;
CycleBound was updated after the node is inserted into priority queue; one
of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
.text
.align 4
.globl _f
_f:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
imull %ecx, %edx
imull %eax, %eax
imull %ecx, %ecx
addl %eax, %ecx
leal (%ecx,%edx,2), %eax
ret
It is also a slight performance win (1% - 3%) for most tests.
llvm-svn: 26470
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llvm-svn: 25895
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chain successors.
llvm-svn: 25630
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llvm-svn: 25613
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llvm-svn: 25604
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llvm-svn: 25601
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llvm-svn: 25544
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