summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* When a node value is only used by a CopyToReg, use the user's dest. This ↵Evan Cheng2007-07-101-50/+55
| | | | | | should not be restricted to nodes that produce only a single value. llvm-svn: 38485
* Change CalculateHeights and CalculateDepths to be non-recursive.Evan Cheng2007-07-061-22/+28
| | | | llvm-svn: 37934
* Pass a SelectionDAG into SDNode::dump everywhere it's used, in preprationDan Gohman2007-06-191-1/+1
| | | | | | | for needing the DAG node to print pre-legalize extended value types, and to get better debug messages with target-specific nodes. llvm-svn: 37656
* Fix some VC++ warnings.Jeff Cohen2007-03-201-0/+1
| | | | llvm-svn: 35224
* Code clean up.Lauro Ramos Venancio2007-03-201-23/+20
| | | | llvm-svn: 35220
* CopyToReg source operand can be a physical register.Lauro Ramos Venancio2007-03-201-3/+19
| | | | llvm-svn: 35213
* print target nodes nicelyChris Lattner2007-02-171-1/+1
| | | | llvm-svn: 34369
* fix indentationChris Lattner2007-02-151-2/+2
| | | | llvm-svn: 34307
* Apply B Scott Michel's patch for PR1184, which improves diagnostics in anChris Lattner2007-02-151-2/+16
| | | | | | abort case. llvm-svn: 34306
* For PR1195:Reid Spencer2007-02-151-1/+1
| | | | | | | Change use of "packed" term to "vector" in comments, strings, variable names, etc. llvm-svn: 34300
* switch the VRBaseMap in the scheduler from an std::map to a DenseMap. ThisChris Lattner2007-02-041-5/+5
| | | | | | speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%). llvm-svn: 33879
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-0/+1
| | | | llvm-svn: 33537
* Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift().Evan Cheng2007-01-241-1/+1
| | | | llvm-svn: 33482
* Remove the DoubleTy special case.Evan Cheng2007-01-221-9/+5
| | | | llvm-svn: 33449
* Compensate for loss of DerivedTypes.h in TargetLowering.hReid Spencer2007-01-121-0/+1
| | | | llvm-svn: 33159
* CopyToReg source operand can be a register as well. e.g. Copy from ↵Evan Cheng2007-01-051-2/+6
| | | | | | GlobalBaseReg. llvm-svn: 32929
* Removing even more <iostream> includes.Bill Wendling2006-12-071-25/+23
| | | | llvm-svn: 32320
* Match TargetInstrInfo changes.Evan Cheng2006-12-011-2/+1
| | | | llvm-svn: 32098
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-2/+2
| | | | | | of opcode and number of operands. llvm-svn: 31947
* Matches MachineInstr changes.Evan Cheng2006-11-131-4/+1
| | | | llvm-svn: 31712
* Add methods to add implicit def use operands to a MI.Evan Cheng2006-11-111-10/+1
| | | | llvm-svn: 31675
* Add implicit def / use operands to MachineInstr.Evan Cheng2006-11-101-0/+12
| | | | llvm-svn: 31633
* Changes to use operand constraints to process two-address instructions.Evan Cheng2006-11-041-4/+9
| | | | llvm-svn: 31453
* handle global address constant sdnodesChris Lattner2006-10-311-2/+7
| | | | llvm-svn: 31323
* Debug tweak.Evan Cheng2006-10-141-2/+2
| | | | llvm-svn: 30959
* Added support for machine specific constantpool values. These are useful forEvan Cheng2006-09-121-5/+9
| | | | | | representing expressions that can only be resolved at link time, etc. llvm-svn: 30278
* Completely eliminate def&use operands. Now a register operand is EITHER aChris Lattner2006-09-051-8/+8
| | | | | | def operand or a use operand. llvm-svn: 30109
* switch the SUnit pred/succ sets from being std::sets to being smallvectors.Chris Lattner2006-08-171-28/+28
| | | | | | | | This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms, a 33% speedup. llvm-svn: 29743
* Reverse the FlaggedNodes after scanning up for flagged preds or else the ↵Evan Cheng2006-08-071-5/+10
| | | | | | order would be reversed. llvm-svn: 29545
* Use an enumeration to eliminate data relocations.Jim Laskey2006-07-211-6/+23
| | | | llvm-svn: 29249
* It was pointed out that DEBUG() is only available with -debug.Jim Laskey2006-07-111-1/+3
| | | | llvm-svn: 29106
* Ensure that dump calls that are associated with asserts are removed fromJim Laskey2006-07-111-1/+1
| | | | | | non-debug build. llvm-svn: 29105
* Instructions with variable operands (variable_ops) can have a number requiredEvan Cheng2006-06-151-1/+2
| | | | | | | | | | | | | operands. e.g. def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops), "call {*}$dst", [(X86call GR32:$dst)]>; TableGen should emit operand informations for the "required" operands. Added a target instruction info flag M_VARIABLE_OPS to indicate the target instruction may have more operands in addition to the minimum required operands. llvm-svn: 28791
* commuteInstruction() does not always create a new MI!Evan Cheng2006-05-311-2/+4
| | | | llvm-svn: 28592
* Eliminate a memory leak.Evan Cheng2006-05-311-0/+1
| | | | llvm-svn: 28585
* lib/Target/Target.tdEvan Cheng2006-05-181-12/+13
| | | | llvm-svn: 28386
* Move function-live-in-handling code from the sdisel code to the scheduler.Chris Lattner2006-05-161-0/+14
| | | | | | | | | This code should be emitted after legalize, so it can't be in sdisel. Note that the EmitFunctionEntryCode hook should be updated to operate on the DAG. The X86 backend is the only one currently using this hook. llvm-svn: 28315
* Fixing 2006-05-01-SchedCausingSpills.ll; some clean upEvan Cheng2006-05-131-6/+6
| | | | llvm-svn: 28279
* Refactor a bunch of includes so that TargetMachine.h doesn't have to includeOwen Anderson2006-05-121-0/+1
| | | | | | | TargetData.h. This should make recompiles a bit faster with my current TargetData tinkering. llvm-svn: 28238
* Duh. That could take a long time.Evan Cheng2006-05-121-11/+15
| | | | llvm-svn: 28235
* Add capability to scheduler to commute nodes for profit.Evan Cheng2006-05-121-7/+15
| | | | | | | If a two-address code whose first operand has uses below, it should be commuted when possible. llvm-svn: 28230
* Refactor scheduler code. Move register-reduction list scheduler to aEvan Cheng2006-05-111-0/+251
| | | | | | | separate file. Added an initial implementation of top-down register pressure reduction list scheduler. llvm-svn: 28226
* Remove and simplify some more machineinstr/machineoperand stuff.Chris Lattner2006-05-041-1/+1
| | | | llvm-svn: 28105
* Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.Chris Lattner2006-05-041-3/+3
| | | | llvm-svn: 28104
* Remove a bunch more SparcV9 specific stuffChris Lattner2006-05-041-5/+5
| | | | llvm-svn: 28093
* Refactor TargetMachine, pushing handling of TargetData into the ↵Owen Anderson2006-05-031-2/+2
| | | | | | | | target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759. llvm-svn: 28074
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-0/+3
| | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. llvm-svn: 27947
* fix spelloChris Lattner2006-03-241-1/+1
| | | | llvm-svn: 27053
* TargetData doesn't know the alignment of vectors :(Chris Lattner2006-03-201-1/+8
| | | | llvm-svn: 26884
* Move some simple-sched-specific instance vars to the simple scheduler.Chris Lattner2006-03-101-3/+0
| | | | llvm-svn: 26690
OpenPOWER on IntegriCloud