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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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* Ensure that dump calls that are associated with asserts are removed fromJim Laskey2006-07-111-1/+1
| | | | | | non-debug build. llvm-svn: 29105
* Instructions with variable operands (variable_ops) can have a number requiredEvan Cheng2006-06-151-1/+2
| | | | | | | | | | | | | operands. e.g. def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops), "call {*}$dst", [(X86call GR32:$dst)]>; TableGen should emit operand informations for the "required" operands. Added a target instruction info flag M_VARIABLE_OPS to indicate the target instruction may have more operands in addition to the minimum required operands. llvm-svn: 28791
* commuteInstruction() does not always create a new MI!Evan Cheng2006-05-311-2/+4
| | | | llvm-svn: 28592
* Eliminate a memory leak.Evan Cheng2006-05-311-0/+1
| | | | llvm-svn: 28585
* lib/Target/Target.tdEvan Cheng2006-05-181-12/+13
| | | | llvm-svn: 28386
* Move function-live-in-handling code from the sdisel code to the scheduler.Chris Lattner2006-05-161-0/+14
| | | | | | | | | This code should be emitted after legalize, so it can't be in sdisel. Note that the EmitFunctionEntryCode hook should be updated to operate on the DAG. The X86 backend is the only one currently using this hook. llvm-svn: 28315
* Fixing 2006-05-01-SchedCausingSpills.ll; some clean upEvan Cheng2006-05-131-6/+6
| | | | llvm-svn: 28279
* Refactor a bunch of includes so that TargetMachine.h doesn't have to includeOwen Anderson2006-05-121-0/+1
| | | | | | | TargetData.h. This should make recompiles a bit faster with my current TargetData tinkering. llvm-svn: 28238
* Duh. That could take a long time.Evan Cheng2006-05-121-11/+15
| | | | llvm-svn: 28235
* Add capability to scheduler to commute nodes for profit.Evan Cheng2006-05-121-7/+15
| | | | | | | If a two-address code whose first operand has uses below, it should be commuted when possible. llvm-svn: 28230
* Refactor scheduler code. Move register-reduction list scheduler to aEvan Cheng2006-05-111-0/+251
| | | | | | | separate file. Added an initial implementation of top-down register pressure reduction list scheduler. llvm-svn: 28226
* Remove and simplify some more machineinstr/machineoperand stuff.Chris Lattner2006-05-041-1/+1
| | | | llvm-svn: 28105
* Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.Chris Lattner2006-05-041-3/+3
| | | | llvm-svn: 28104
* Remove a bunch more SparcV9 specific stuffChris Lattner2006-05-041-5/+5
| | | | llvm-svn: 28093
* Refactor TargetMachine, pushing handling of TargetData into the ↵Owen Anderson2006-05-031-2/+2
| | | | | | | | target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759. llvm-svn: 28074
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-0/+3
| | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. llvm-svn: 27947
* fix spelloChris Lattner2006-03-241-1/+1
| | | | llvm-svn: 27053
* TargetData doesn't know the alignment of vectors :(Chris Lattner2006-03-201-1/+8
| | | | llvm-svn: 26884
* Move some simple-sched-specific instance vars to the simple scheduler.Chris Lattner2006-03-101-3/+0
| | | | llvm-svn: 26690
* prune #includesChris Lattner2006-03-101-5/+0
| | | | llvm-svn: 26689
* move some simple scheduler methods into the simple schedulerChris Lattner2006-03-101-235/+0
| | | | llvm-svn: 26688
* Make EmitNode take a SDNode instead of a NodeInfo*Chris Lattner2006-03-101-4/+3
| | | | llvm-svn: 26687
* Move the VRBase field from NodeInfo to being a separate, explicit, map.Chris Lattner2006-03-101-11/+24
| | | | llvm-svn: 26686
* Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchyChris Lattner2006-03-101-4/+0
| | | | llvm-svn: 26682
* Change the interface for getting a target HazardRecognizer to be more clean.Chris Lattner2006-03-081-1/+1
| | | | llvm-svn: 26608
* When a hazard recognizer needs noops to be inserted, do so. This representsChris Lattner2006-03-051-0/+4
| | | | | | noops as null pointers in the instruction sequence. llvm-svn: 26564
* Added an offset field to ConstantPoolSDNode.Evan Cheng2006-02-251-1/+2
| | | | llvm-svn: 26371
* Pass all the flags to the asm printer, not just the # operands.Chris Lattner2006-02-241-1/+1
| | | | llvm-svn: 26362
* rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.Chris Lattner2006-02-241-5/+11
| | | | | | Add support for addressing modes. llvm-svn: 26361
* Refactor operand adding out to a new AddOperand methodChris Lattner2006-02-241-66/+81
| | | | llvm-svn: 26358
* Record all of the expanded registers in the DAG and machine instr, fixingChris Lattner2006-02-231-11/+20
| | | | | | several bugs in inline asm expanded operands. llvm-svn: 26332
* Make MachineConstantPool entries alignments explicitChris Lattner2006-02-091-2/+12
| | | | llvm-svn: 26071
* Fix VC++ warning.Jeff Cohen2006-02-041-1/+0
| | | | llvm-svn: 25975
* Get rid of some memory leaks identified by ValgrindEvan Cheng2006-02-041-2/+8
| | | | llvm-svn: 25960
* Add initial support for immediates. This allows us to compile this:Chris Lattner2006-02-041-5/+15
| | | | | | | | | | | | | | | | | | int %rlwnm(int %A, int %B) { %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17) ret int %C } into: _rlwnm: or r2, r3, r3 or r3, r4, r4 rlwnm r2, r2, r3, 4, 17 ;; note the immediates :) or r3, r2, r2 blr llvm-svn: 25955
* Allow the specification of explicit alignments for constant pool entries.Evan Cheng2006-01-311-1/+2
| | | | llvm-svn: 25855
* Handle physreg input/outputs. We now compile this:Chris Lattner2006-01-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int %test_cpuid(int %op) { %B = alloca int %C = alloca int %D = alloca int %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op) %Bv = load int* %B %Cv = load int* %C %Dv = load int* %D %x = add int %A, %Bv %y = add int %x, %Cv %z = add int %y, %Dv ret int %z } to this: _test_cpuid: sub %ESP, 16 mov DWORD PTR [%ESP], %EBX mov %EAX, DWORD PTR [%ESP + 20] cpuid mov DWORD PTR [%ESP + 8], %ECX mov DWORD PTR [%ESP + 12], %EBX mov DWORD PTR [%ESP + 4], %EDX mov %ECX, DWORD PTR [%ESP + 12] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 8] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 4] add %EAX, %ECX mov %EBX, DWORD PTR [%ESP] add %ESP, 16 ret ... note the proper register allocation. :) it is unclear to me why the loads aren't folded into the adds. llvm-svn: 25827
* Teach the scheduler to emit the appropriate INLINEASM MachineInstr for anChris Lattner2006-01-261-0/+29
| | | | | | ISD::INLINEASM node. llvm-svn: 25668
* No need to keep track of top and bottom nodes in a group since the vector isEvan Cheng2006-01-251-5/+0
| | | | | | already in order. Thanks Jim for pointing it out. llvm-svn: 25608
* Keep track of bottom / top element of a set of flagged nodes.Evan Cheng2006-01-251-1/+6
| | | | llvm-svn: 25600
* Factor out more instruction scheduler code to the base class.Evan Cheng2006-01-231-6/+234
| | | | llvm-svn: 25532
* Do some code refactoring on Jim's scheduler in preparation of the new listEvan Cheng2006-01-211-1127/+24
| | | | | | scheduler. llvm-svn: 25493
* purity++Duraid Madina2005-12-291-0/+1
| | | | llvm-svn: 25041
* Disengage DEBUG_LOC from non-PPC targets.Jim Laskey2005-12-211-1/+1
| | | | llvm-svn: 24919
* Amend comment.Jim Laskey2005-12-191-1/+2
| | | | llvm-svn: 24861
* Create a strong dependency for loads following stores. This will leave aJim Laskey2005-12-191-2/+6
| | | | | | latency period between the two. llvm-svn: 24860
* Keep VC++ happy.Jeff Cohen2005-12-181-0/+1
| | | | llvm-svn: 24835
* Fix a bug Sabre was having where the DAG root was a group. The group dominatorJim Laskey2005-12-181-1/+6
| | | | | | needed to be added to the ordering list, not the first member of the group. llvm-svn: 24816
* Groups were not emitted if the dominator node and the node in the ordering listJim Laskey2005-12-181-10/+6
| | | | | | were not the same node. Ultimately the test was bogus. llvm-svn: 24815
* Simplify codeChris Lattner2005-12-181-7/+2
| | | | llvm-svn: 24806
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