summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Commit message (Collapse)AuthorAgeFilesLines
* fix spelloChris Lattner2006-03-241-1/+1
| | | | llvm-svn: 27053
* TargetData doesn't know the alignment of vectors :(Chris Lattner2006-03-201-1/+8
| | | | llvm-svn: 26884
* Move some simple-sched-specific instance vars to the simple scheduler.Chris Lattner2006-03-101-3/+0
| | | | llvm-svn: 26690
* prune #includesChris Lattner2006-03-101-5/+0
| | | | llvm-svn: 26689
* move some simple scheduler methods into the simple schedulerChris Lattner2006-03-101-235/+0
| | | | llvm-svn: 26688
* Make EmitNode take a SDNode instead of a NodeInfo*Chris Lattner2006-03-101-4/+3
| | | | llvm-svn: 26687
* Move the VRBase field from NodeInfo to being a separate, explicit, map.Chris Lattner2006-03-101-11/+24
| | | | llvm-svn: 26686
* Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchyChris Lattner2006-03-101-4/+0
| | | | llvm-svn: 26682
* Change the interface for getting a target HazardRecognizer to be more clean.Chris Lattner2006-03-081-1/+1
| | | | llvm-svn: 26608
* When a hazard recognizer needs noops to be inserted, do so. This representsChris Lattner2006-03-051-0/+4
| | | | | | noops as null pointers in the instruction sequence. llvm-svn: 26564
* Added an offset field to ConstantPoolSDNode.Evan Cheng2006-02-251-1/+2
| | | | llvm-svn: 26371
* Pass all the flags to the asm printer, not just the # operands.Chris Lattner2006-02-241-1/+1
| | | | llvm-svn: 26362
* rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.Chris Lattner2006-02-241-5/+11
| | | | | | Add support for addressing modes. llvm-svn: 26361
* Refactor operand adding out to a new AddOperand methodChris Lattner2006-02-241-66/+81
| | | | llvm-svn: 26358
* Record all of the expanded registers in the DAG and machine instr, fixingChris Lattner2006-02-231-11/+20
| | | | | | several bugs in inline asm expanded operands. llvm-svn: 26332
* Make MachineConstantPool entries alignments explicitChris Lattner2006-02-091-2/+12
| | | | llvm-svn: 26071
* Fix VC++ warning.Jeff Cohen2006-02-041-1/+0
| | | | llvm-svn: 25975
* Get rid of some memory leaks identified by ValgrindEvan Cheng2006-02-041-2/+8
| | | | llvm-svn: 25960
* Add initial support for immediates. This allows us to compile this:Chris Lattner2006-02-041-5/+15
| | | | | | | | | | | | | | | | | | int %rlwnm(int %A, int %B) { %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17) ret int %C } into: _rlwnm: or r2, r3, r3 or r3, r4, r4 rlwnm r2, r2, r3, 4, 17 ;; note the immediates :) or r3, r2, r2 blr llvm-svn: 25955
* Allow the specification of explicit alignments for constant pool entries.Evan Cheng2006-01-311-1/+2
| | | | llvm-svn: 25855
* Handle physreg input/outputs. We now compile this:Chris Lattner2006-01-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int %test_cpuid(int %op) { %B = alloca int %C = alloca int %D = alloca int %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op) %Bv = load int* %B %Cv = load int* %C %Dv = load int* %D %x = add int %A, %Bv %y = add int %x, %Cv %z = add int %y, %Dv ret int %z } to this: _test_cpuid: sub %ESP, 16 mov DWORD PTR [%ESP], %EBX mov %EAX, DWORD PTR [%ESP + 20] cpuid mov DWORD PTR [%ESP + 8], %ECX mov DWORD PTR [%ESP + 12], %EBX mov DWORD PTR [%ESP + 4], %EDX mov %ECX, DWORD PTR [%ESP + 12] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 8] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 4] add %EAX, %ECX mov %EBX, DWORD PTR [%ESP] add %ESP, 16 ret ... note the proper register allocation. :) it is unclear to me why the loads aren't folded into the adds. llvm-svn: 25827
* Teach the scheduler to emit the appropriate INLINEASM MachineInstr for anChris Lattner2006-01-261-0/+29
| | | | | | ISD::INLINEASM node. llvm-svn: 25668
* No need to keep track of top and bottom nodes in a group since the vector isEvan Cheng2006-01-251-5/+0
| | | | | | already in order. Thanks Jim for pointing it out. llvm-svn: 25608
* Keep track of bottom / top element of a set of flagged nodes.Evan Cheng2006-01-251-1/+6
| | | | llvm-svn: 25600
* Factor out more instruction scheduler code to the base class.Evan Cheng2006-01-231-6/+234
| | | | llvm-svn: 25532
* Do some code refactoring on Jim's scheduler in preparation of the new listEvan Cheng2006-01-211-1127/+24
| | | | | | scheduler. llvm-svn: 25493
* purity++Duraid Madina2005-12-291-0/+1
| | | | llvm-svn: 25041
* Disengage DEBUG_LOC from non-PPC targets.Jim Laskey2005-12-211-1/+1
| | | | llvm-svn: 24919
* Amend comment.Jim Laskey2005-12-191-1/+2
| | | | llvm-svn: 24861
* Create a strong dependency for loads following stores. This will leave aJim Laskey2005-12-191-2/+6
| | | | | | latency period between the two. llvm-svn: 24860
* Keep VC++ happy.Jeff Cohen2005-12-181-0/+1
| | | | llvm-svn: 24835
* Fix a bug Sabre was having where the DAG root was a group. The group dominatorJim Laskey2005-12-181-1/+6
| | | | | | needed to be added to the ordering list, not the first member of the group. llvm-svn: 24816
* Groups were not emitted if the dominator node and the node in the ordering listJim Laskey2005-12-181-10/+6
| | | | | | were not the same node. Ultimately the test was bogus. llvm-svn: 24815
* Simplify codeChris Lattner2005-12-181-7/+2
| | | | llvm-svn: 24806
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-1/+1
| | | | | | work. This change has no effect on generated code. llvm-svn: 24563
* Added an index field to GlobalAddressSDNode so it can represent X+12, etc.Evan Cheng2005-11-301-1/+1
| | | | llvm-svn: 24523
* Switch the allnodes list from a vector of pointers to an ilist of nodes.This ↵Chris Lattner2005-11-091-11/+8
| | | | | | | | eliminates the vector, allows constant time removal of a node froma graph, and makes iteration over the all nodes list stable when adding nodes to the graph. llvm-svn: 24263
* Explicitly initialize some instance varsChris Lattner2005-11-081-4/+5
| | | | llvm-svn: 24247
* Let's try ignoring resource utilization on the backward pass.Jim Laskey2005-11-071-0/+2
| | | | llvm-svn: 24231
* Fix logic bug in finding retry slot in tally.Jim Laskey2005-11-051-15/+33
| | | | llvm-svn: 24188
* Fix a warningJim Laskey2005-11-041-0/+1
| | | | llvm-svn: 24187
* Scheduling now uses itinerary data.Jim Laskey2005-11-041-166/+201
| | | | llvm-svn: 24180
* 1. Embed and not inherit vector for NodeGroup.Jim Laskey2005-10-311-20/+39
| | | | | | | | 2. Iterate operands and not uses (performance.) 3. Some long pending comment changes. llvm-svn: 24119
* Reduce the number of copies emitted as machine instructions byChris Lattner2005-10-301-16/+57
| | | | | | | | | | | | | | | | | generating results in vregs that will need them. In the case of something like this: CopyToReg((add X, Y), reg1024), we no longer emit code like this: reg1025 = add X, Y reg1024 = reg 1025 Instead, we emit: reg1024 = add X, Y Whoa! :) llvm-svn: 24111
* Inhibit instructions from being pushed before function calls. This willJim Laskey2005-10-131-3/+55
| | | | | | minimize unnecessary spilling. llvm-svn: 23710
* Finally committing to the new scheduler. Still -sched=none by default.Jim Laskey2005-10-121-249/+125
| | | | llvm-svn: 23702
* When emiting a CopyFromReg and the source is already a vreg, do not botherChris Lattner2005-10-091-27/+31
| | | | | | | | | | | creating a new vreg and inserting a copy: just use the input vreg directly. This speeds up the compile (e.g. about 5% on mesa with a debug build of llc) by not adding a bunch of copies and vregs to be coallesced away. On mesa, for example, this reduces the number of intervals from 168601 to 129040 going into the coallescer. llvm-svn: 23671
* Reverting to version - until problem isolated.Jim Laskey2005-10-041-70/+238
| | | | llvm-svn: 23622
* Refactor gathering node info and emission.Jim Laskey2005-10-031-238/+70
| | | | llvm-svn: 23610
* silence a bogus warningChris Lattner2005-10-021-1/+1
| | | | llvm-svn: 23595
OpenPOWER on IntegriCloud