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* Add support for other relocation bases to jump tables, as well as custom asm ↵Andrew Lenharth2006-09-241-0/+11
| | | | | | directives llvm-svn: 30593
* Expand 64-bit shifts more optimally if we know that the high bit of theChris Lattner2006-09-201-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | shift amount is one or zero. For example, for: long long foo1(long long X, int C) { return X << (C|32); } long long foo2(long long X, int C) { return X << (C&~32); } we get: _foo1: movb $31, %cl movl 4(%esp), %edx andb 12(%esp), %cl shll %cl, %edx xorl %eax, %eax ret _foo2: movb $223, %cl movl 4(%esp), %eax movl 8(%esp), %edx andb 12(%esp), %cl shldl %cl, %eax, %edx shll %cl, %eax ret instead of: _foo1: subl $4, %esp movl %ebx, (%esp) movb $32, %bl movl 8(%esp), %eax movl 12(%esp), %edx movb %bl, %cl orb 16(%esp), %cl shldl %cl, %eax, %edx shll %cl, %eax xorl %ecx, %ecx testb %bl, %bl cmovne %eax, %edx cmovne %ecx, %eax movl (%esp), %ebx addl $4, %esp ret _foo2: subl $4, %esp movl %ebx, (%esp) movb $223, %cl movl 8(%esp), %eax movl 12(%esp), %edx andb 16(%esp), %cl shldl %cl, %eax, %edx shll %cl, %eax xorl %ecx, %ecx xorb %bl, %bl testb %bl, %bl cmovne %eax, %edx cmovne %ecx, %eax movl (%esp), %ebx addl $4, %esp ret llvm-svn: 30506
* Fix a typo.Evan Cheng2006-09-181-3/+2
| | | | llvm-svn: 30474
* Allow i32 UDIV, SDIV, UREM, SREM to be expanded into libcalls.Evan Cheng2006-09-181-6/+30
| | | | llvm-svn: 30470
* Oh yeah, this is needed tooChris Lattner2006-09-161-3/+3
| | | | llvm-svn: 30407
* simplify control flow, no functionality changeChris Lattner2006-09-161-6/+12
| | | | llvm-svn: 30403
* Allow custom expand of mulChris Lattner2006-09-161-0/+9
| | | | llvm-svn: 30402
* Compile X << 1 (where X is a long-long) to:Chris Lattner2006-09-131-7/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | addl %ecx, %ecx adcl %eax, %eax instead of: movl %ecx, %edx addl %edx, %edx shrl $31, %ecx addl %eax, %eax orl %ecx, %eax and to: addc r5, r5, r5 adde r4, r4, r4 instead of: slwi r2,r9,1 srwi r0,r11,31 slwi r3,r11,1 or r2,r0,r2 on PPC. llvm-svn: 30284
* Implement the fpowi now by lowering to a libcallChris Lattner2006-09-091-1/+8
| | | | llvm-svn: 30225
* Allow targets to custom lower expanded BIT_CONVERT'sChris Lattner2006-09-091-2/+15
| | | | llvm-svn: 30217
* Allow legalizer to expand ISD::MUL using only MULHS in the rare case that isEvan Cheng2006-09-011-6/+13
| | | | | | possible and the target only supports MULHS. llvm-svn: 30022
* s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|Chris Lattner2006-08-271-1/+1
| | | | llvm-svn: 29911
* Fix PR861Chris Lattner2006-08-211-0/+1
| | | | llvm-svn: 29796
* eliminate use of getNode that takes vector of valuetypes.Chris Lattner2006-08-141-9/+8
| | | | llvm-svn: 29687
* Start eliminating temporary vectors used to create DAG nodes. Instead, passChris Lattner2006-08-081-40/+47
| | | | | | | | | | | | | | | | | | | in the start of an array and a count of operands where applicable. In many cases, the number of operands is known, so this static array can be allocated on the stack, avoiding the heap. In many other cases, a SmallVector can be used, which has the same benefit in the common cases. I updated a lot of code calling getNode that takes a vector, but ran out of time. The rest of the code should be updated, and these methods should be removed. We should also do the same thing to eliminate the methods that take a vector of MVT::ValueTypes. It would be extra nice to convert the dagiselemitter to avoid creating vectors for operands when calling getTargetNode. llvm-svn: 29566
* Eliminate some malloc traffic by allocating vectors on the stack. Change someChris Lattner2006-08-081-21/+23
| | | | | | | | | method that took std::vector<SDOperand> to take a pointer to a first operand and #operands. This speeds up isel on kc++ by about 3%. llvm-svn: 29561
* Make SelectionDAG::RemoveDeadNodes iterative instead of recursive, whichChris Lattner2006-08-041-1/+1
| | | | | | also make it simpler. llvm-svn: 29524
* Fix a case where LegalizeAllNodesNotLeadingTo could take exponential time.Chris Lattner2006-07-261-6/+21
| | | | | | | | This manifested itself as really long time to compile Regression/CodeGen/Generic/2003-05-28-ManyArgs.ll on ppc. This is PR847. llvm-svn: 29313
* Ensure that dump calls that are associated with asserts are removed fromJim Laskey2006-07-111-1/+13
| | | | | | non-debug build. llvm-svn: 29105
* Fix CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll and PR818.Chris Lattner2006-07-111-12/+29
| | | | llvm-svn: 29099
* Mark these two classes as hidden, shrinking libllbmgcc.dylib by 25KChris Lattner2006-06-281-1/+2
| | | | llvm-svn: 28970
* Change RET node to include signness information of the return values. e.g.Evan Cheng2006-05-261-8/+12
| | | | | | RET chain, value1, sign1, value2, sign2 llvm-svn: 28509
* Patches to make the LLVM sources more -pedantic clean. Patch providedChris Lattner2006-05-241-1/+1
| | | | | | by Anton Korobeynikov! This is a step towards closing PR786. llvm-svn: 28447
* When we legalize target nodes, do not use getNode to create a new node,Chris Lattner2006-05-171-13/+4
| | | | | | | | | | | | use UpdateNodeOperands to just update the operands! This is important because getNode will allocate a new node if the node returns a flag and this breaks assumptions in the legalizer that you can legalize some things multiple times and get exactly the same results. This latent bug was exposed by my ppc patch last night, and this fixes gsm/toast. llvm-svn: 28348
* Add an assertion, avoid some unneeded work for each call. No functionalityChris Lattner2006-05-171-6/+10
| | | | | | change. llvm-svn: 28347
* Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallToChris Lattner2006-05-161-2/+3
| | | | | | produce it. llvm-svn: 28338
* Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them onceChris Lattner2006-05-161-2/+11
| | | | | | for each argument. llvm-svn: 28313
* Merge identical code.Chris Lattner2006-05-131-8/+0
| | | | llvm-svn: 28274
* Fix PR773Nate Begeman2006-05-091-2/+20
| | | | llvm-svn: 28207
* Refactor TargetMachine, pushing handling of TargetData into the ↵Owen Anderson2006-05-031-3/+3
| | | | | | | | target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759. llvm-svn: 28074
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-2/+18
| | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. llvm-svn: 27947
* Simplify some codeChris Lattner2006-04-191-5/+1
| | | | llvm-svn: 27846
* Fix handling of calls in functions that use vectors. This fixes a crash onChris Lattner2006-04-171-13/+1
| | | | | | the code in GCC PR26546. llvm-svn: 27780
* Codegen insertelement with constant insertion points as scalar_to_vectorChris Lattner2006-04-171-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and a shuffle. For this: void %test2(<4 x float>* %F, float %f) { %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2] %tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1] %tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2 ; <<4 x float>> [#uses=2] %tmp6 = add <4 x float> %tmp2, %tmp2 ; <<4 x float>> [#uses=1] store <4 x float> %tmp6, <4 x float>* %F ret void } we now get this on X86 (which will get better): _test2: movl 4(%esp), %eax movaps (%eax), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, %xmm1 shufps $3, %xmm1, %xmm1 movaps %xmm0, %xmm2 shufps $1, %xmm2, %xmm2 unpcklps %xmm1, %xmm2 movss 8(%esp), %xmm1 unpcklps %xmm1, %xmm0 unpcklps %xmm2, %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%eax) ret instead of: _test2: subl $28, %esp movl 32(%esp), %eax movaps (%eax), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%esp) movss 36(%esp), %xmm0 movss %xmm0, 8(%esp) movaps (%esp), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%eax) addl $28, %esp ret llvm-svn: 27765
* Add support for promoting stores from one legal type to another, allowing usChris Lattner2006-04-161-0/+8
| | | | | | to write one pattern for vector stores instead of 4. llvm-svn: 27730
* Make this assertion betterChris Lattner2006-04-141-1/+1
| | | | llvm-svn: 27695
* Promote vector AND, OR, and XOREvan Cheng2006-04-121-0/+27
| | | | llvm-svn: 27632
* Vector type promotion for ISD::LOAD and ISD::SELECTEvan Cheng2006-04-121-9/+23
| | | | llvm-svn: 27606
* Implement support for the formal_arguments node. To get this, targets ↵Chris Lattner2006-04-121-3/+8
| | | | | | shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload llvm-svn: 27604
* Only get Tmp2 for cases where number of operands is > 1. Fixed return void.Evan Cheng2006-04-111-1/+1
| | | | llvm-svn: 27586
* add some todosChris Lattner2006-04-111-0/+8
| | | | llvm-svn: 27580
* Add basic support for legalizing returns of vectorsChris Lattner2006-04-111-9/+36
| | | | llvm-svn: 27578
* Missing breakEvan Cheng2006-04-101-0/+1
| | | | llvm-svn: 27559
* Add code generator support for VSELECTChris Lattner2006-04-081-0/+5
| | | | llvm-svn: 27542
* Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patternsChris Lattner2006-04-081-2/+14
| | | | | | to match again :) llvm-svn: 27533
* add a sanity check: LegalizeOp should return a value that is the same typeChris Lattner2006-04-081-0/+3
| | | | | | as its input. llvm-svn: 27528
* INSERT_VECTOR_ELT lowering bug:Evan Cheng2006-04-081-14/+11
| | | | | | | | | store vector to $esp store element to $esp + sizeof(VT) * index load vector from $esp The bug is VT is the type of the vector element, not the type of the vector! llvm-svn: 27517
* Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expandedEvan Cheng2006-04-051-2/+30
| | | | | | or custom lowering fails. llvm-svn: 27432
* * Add supprot for SCALAR_TO_VECTOR operations where the input needs to beChris Lattner2006-04-041-21/+102
| | | | | | | | | | promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC). * Add support for targets to request that VECTOR_SHUFFLE nodes be promoted to a canonical type, for example, we only want v16i8 shuffles on PPC. * Move isShuffleLegal out of TLI into Legalize. * Teach isShuffleLegal to allow shuffles that need to be promoted. llvm-svn: 27399
* Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to ↵Chris Lattner2006-04-021-16/+27
| | | | | | work with PowerPC. llvm-svn: 27349
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