| Commit message (Collapse) | Author | Age | Files | Lines | 
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operands are themselves vectors. Based on a patch by
Micah Villmow for PR6338.
llvm-svn: 97165
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terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.
llvm-svn: 97137
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the number of value bits, not the number of bits of allocation for in-memory
storage.
Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.
Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.
This fixes PR1784.
llvm-svn: 97064
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llvm-svn: 96240
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llvm-svn: 95781
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1. MachineJumpTableInfo is now created lazily for a function the first time
   it actually makes a jump table instead of for every function.
2. The encoding of jump table entries is now described by the
   MachineJumpTableInfo::JTEntryKind enum.  This enum is determined by the
   TLI::getJumpTableEncoding() hook, instead of by lots of code scattered
   throughout the compiler that "knows" that jump table entries are always
   32-bits in pic mode (for example).
3. The size and alignment of jump table entries is now calculated based on
   their kind, instead of at machinefunction creation time.
Future work includes using the EntryKind in more places in the compiler,
eliminating other logic that "knows" the layout of jump tables in various
situations.
llvm-svn: 94470
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the alignment allows.  Fixed a bug where we didn't use a
vector load/store for PR5626.
llvm-svn: 94338
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really does need to be a vector type, because
TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type,
and it needs to be able to distinguish between vectors and scalars.
Also, fix some more issues with legalization of vector casts.
llvm-svn: 93043
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llvm-svn: 92575
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llvm-svn: 92188
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llvm-svn: 92011
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llvm-svn: 91953
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llvm-svn: 91949
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is finished.
llvm-svn: 91942
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was using "Tmp1" in the first getNode call instead of Node->getOperand(0).
llvm-svn: 91936
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return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
llvm-svn: 91880
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LegalizeDAG.cpp. Unlike the code it replaces, which simply decrements the simple
type by one, getHalfSizedIntegerVT() searches for the smallest simple integer
type that is at least half the size of the type it is called on. This approach
has the advantage that it will continue working if a new value type (such as
i24) is added to MVT.
Also, in preparation for new value types, remove the assertions that
non-power-of-2 8-bit-mutiple types are Extended when legalizing extload and
truncstore operations.
llvm-svn: 91614
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a vector type.
llvm-svn: 91181
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llvm-svn: 91158
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llvm-svn: 90668
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Patch by Howard Hinnant!
llvm-svn: 90365
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Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
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llvm-svn: 89536
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and stores, handle the case where the element size is not
a valid target type correctly (PPC).
llvm-svn: 89521
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constant whose component type is not a legal type for the target.
(If the target ConstantPool cannot handle this type either, it has
an opportunity to merge elements.  In practice any target with
8-bit bytes must support i8 *as data*).  7320806 (partial).
llvm-svn: 86751
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llvm-svn: 86384
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llvm-svn: 85361
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returns true if the fp immediate can be natively codegened by target.
llvm-svn: 85281
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VISIBILITY_HIDDEN removal.
llvm-svn: 85043
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Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
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stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
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PseudoSourceValue.
llvm-svn: 84411
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llvm-svn: 84321
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necessarily fixed. Only those will negative frame indices are "fixed."
llvm-svn: 84315
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llvm-svn: 84300
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llvm-svn: 83182
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Use MDNodes to encode debug info in llvm IR.
llvm-svn: 80406
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llvm-svn: 80116
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llvm-svn: 80073
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llvm.dbg.... global variables, to encode debugging information in llvm IR. This is mostly a mechanical change that tests metadata support very well.
This change speeds up llvm-gcc by more then 6% at "-O0 -g" (measured by compiling InstructionCombining.cpp!)
llvm-svn: 79977
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update all code that this affects.
llvm-svn: 79830
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llvm-svn: 79742
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just falling through the end.
llvm-svn: 79383
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SRA_PARTS, as is done for SRL, SHL, and SRA.
llvm-svn: 79380
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llvm-svn: 79133
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llvm-svn: 79087
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libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
llvm-svn: 79033
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llvm-svn: 78948
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infrastructure work needed to get the contexts to where they need to be first.
llvm-svn: 78759
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while
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
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