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* Set the isTied flags when building INLINEASM MachineInstrs.Jakob Stoklund Olesen2012-08-291-4/+21
| | | | | | | | For normal instructions, isTied() is set automatically by addOperand(), based on MCInstrDesc, but inline asm has tied operands outside the descriptor. llvm-svn: 162869
* Avoid including explicit uses when counting SDNode imp-uses.Jakob Stoklund Olesen2012-08-241-3/+6
| | | | | | | It is legal to have a register node as an explicit operand, it shouldn't be counted as an implicit use. llvm-svn: 162591
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-071-0/+4
| | | | | | | This adds support for TargetIndex operands during isel. The meaning of these (index, offset, flags) operands is entirely defined by the target. llvm-svn: 161453
* InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:Evan Cheng2012-07-111-1/+2
| | | | | | | | | | | | | | | | | r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to a copy: r1026 = copy r1024 This is correct. However it uses TII->isCoalescableExtInstr() which can return true for instructions which essentially does a sext_in_reg so this can end up with an illegal copy where the source and destination register classes do not match. Add a check to avoid it. Sorry, no test case possible at this time. rdar://11849816 llvm-svn: 160059
* Allow trailing physreg RegisterSDNode operands on non-variadic instructions.Jakob Stoklund Olesen2012-07-041-7/+27
| | | | | | | | | | | | | | | Also allow trailing register mask operands on non-variadic both MachineSDNodes and MachineInstrs. The extra physreg RegisterSDNode operands are added to the MI as <imp-use> operands. This makes it possible to have non-variadic call instructions. Call and return instructions really are non-variadic, the argument registers should only be used implicitly - they are not part of the encoding. llvm-svn: 159727
* Clear kill flags in InstrEmitter::EmitSubregNode().Jakob Stoklund Olesen2012-06-291-0/+1
| | | | | | | When a local virtual register is made global, make sure to clear any existing kill flags. llvm-svn: 159461
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-3/+3
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-031-6/+10
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
* Don't crash when a glue node contains an internal CopyToRegHal Finkel2012-02-241-0/+3
| | | | | | | This is necessary to support the existing ppc lowering code for indirect calls. Fixes PR12071. llvm-svn: 151373
* Handle all live physreg defs in the same place.Jakob Stoklund Olesen2012-02-031-43/+46
| | | | | | | | | | | SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. llvm-svn: 149708
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-2/+0
| | | | llvm-svn: 148578
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-181-0/+2
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
* Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper2012-01-181-7/+12
| | | | | | TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE llvm-svn: 148377
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen2011-10-051-27/+46
| | | | | | | | | | | | EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. llvm-svn: 141207
* Simplify INSERT_SUBREG emission.Jakob Stoklund Olesen2011-10-051-27/+19
| | | | | | | | | | | | | | The register class created by INSERT_SUBREG and SUBREG_TO_REG must be legal and support the SubIdx sub-registers. The new getSubClassWithSubReg() hook can compute that. This may create INSERT_SUBREG instructions defining a larger register class than the sub-register being inserted. That is OK, RegisterCoalescer will constrain the register class as needed when it eliminates the INSERT_SUBREG instructions. llvm-svn: 141198
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-301-1/+2
| | | | | | It will soon need the context. llvm-svn: 140896
* Constrain register classes instead of emitting copies.Jakob Stoklund Olesen2011-09-221-3/+5
| | | | | | | | | | | Sometimes register class constraints are trivial, like GR32->GR32_NOSP, or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual register instead of emitting a copy in these cases. Normally, these copies are handled by the coalescer. This saves some coalescer work. llvm-svn: 140340
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-211-0/+2
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-1/+2
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-2/+1
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* whitespaceAndrew Trick2011-09-201-26/+26
| | | | llvm-svn: 140133
* Follow up to r138791.Evan Cheng2011-08-301-0/+4
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-1/+1
| | | | llvm-svn: 135375
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-16/+16
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-3/+3
| | | | llvm-svn: 133944
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. llvm-svn: 133902
* Handle debug info for i128 constants.Devang Patel2011-06-241-6/+2
| | | | llvm-svn: 133821
* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-161-2/+7
| | | | | | | | | | In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> llvm-svn: 133210
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its ↵Owen Anderson2011-06-161-5/+6
| | | | | | | | first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change. This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. llvm-svn: 133178
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-021-1/+1
| | | | | | No functional change. llvm-svn: 132455
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-1/+1
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-4/+4
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Optimize:Evan Cheng2011-01-051-23/+39
| | | | | | | | | r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to: r1026 = copy r1024 llvm-svn: 122925
* flags -> glue for selectiondagChris Lattner2010-12-231-10/+10
| | | | llvm-svn: 122509
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-231-6/+6
| | | | | | | new gcc warning that complains on self-assignments and self-initializations. llvm-svn: 122458
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-9/+9
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-171-3/+1
| | | | | | Radar 8776599 llvm-svn: 122018
* Reword comment slightly.Eric Christopher2010-12-081-1/+1
| | | | llvm-svn: 121293
* Split pseudo-instruction expansion into a separate pass, to make itDan Gohman2010-11-161-13/+0
| | | | | | | easier to debug, and to avoid complications when the CFG changes in the middle of the instruction selection process. llvm-svn: 119382
* Revert r112461. It was failing on PPC...Bill Wendling2010-08-301-4/+2
| | | | llvm-svn: 112463
* When adding a register, we should mark it as "def" if it can optionally defineBill Wendling2010-08-301-2/+4
| | | | | | said (physical) register. llvm-svn: 112461
* Emit COPY instructions instead of using copyRegToReg in InstrEmitter,Jakob Stoklund Olesen2010-07-101-34/+9
| | | | | | | | | ScheduleDAGEmit, TwoAddressLowering, and PHIElimination. This switches the bulk of register copies to using COPY, but many less used copyRegToReg calls remain. llvm-svn: 108050
* Insert IMPLICIT_DEF instructions at the current insert position, notDan Gohman2010-07-101-1/+1
| | | | | | at the end of the block. llvm-svn: 108045
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-2/+7
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-091-2/+7
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-081-7/+9
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-5/+2
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* Not all custom inserters create new basic blocks. If the inserterDan Gohman2010-07-071-2/+5
| | | | | | didn't create a new block, don't reset the insert position. llvm-svn: 107813
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